SC68C652BIB48,157 NXP Semiconductors, SC68C652BIB48,157 Datasheet - Page 23

• Manufacturer Part Number: SC68C652BIB48,157
• Description: IC UART DUAL 48LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC68C652BIB48,157

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LFQFP
• Voltage: 2.25 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278766157; SC68C652BIB48; SC68C652BIB48

NXP Semiconductors
SC68C652B_2
Product data sheet
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20.
Bit
7
6
5
4
3
2
1
0
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register bits description
Description
Clock select
IR enable (see
reserved; set to ‘0’
Loopback. Enable the local loopback mode (diagnostics). In this mode the
transmitter output (TXn) and the receiver input (RXn), CTSn, DSRn, CDn,
and RIn pins are disconnected from the SC68C652B I/O pins. Internally
the modem data and control pins are connected into a loopback data
configuration (see
interrupts remain fully operational. The Modem Control Interrupts are also
operational, but the interrupts’ sources are switched to the lower four bits of
the Modem Control. Interrupts continue to be controlled by the IER
register.
OP2 control
(OP1). OP1A/OP1B are not available as an external signal in the
SC68C652B. This bit is instead used in the loopback mode only. In the
loopback mode, this bit is used to write the state of the modem RIn pin
interface signal.
RTS
DTR
Rev. 02 — 2 November 2009
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While
in this mode, the TXn/RXn output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the
IrDA infrared interface requirement. As such, while in this mode, the
infrared TXn output will be a logic 0 during idle data conditions.
logic 0 = disable loopback mode (normal default condition)
logic 1 = enable local loopback mode (diagnostics)
logic 0 = forces OP2n output pin to HIGH state
logic 1 = forces OP2n output pin to LOW state. In loopback mode,
controls MSR[7].
logic 0 = force RTSn output pin to a logic 1 (normal default condition)
logic 1 = force RTSn output pin to a logic 0
logic 0 = force DTRn output pin to a logic 1 (normal default condition)
logic 1 = force DTRn output pin to a logic 0
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Figure
Figure
16)
4). In this mode, the receiver and transmitter
SC68C652B
© NXP B.V. 2009. All rights reserved.
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