SC16C750IA44,512 NXP Semiconductors, SC16C750IA44,512 Datasheet - Page 11

• Manufacturer Part Number: SC16C750IA44,512
• Description: IC UART 64BYTE 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C750IA44,512

• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 2.25 V ~ 5.5 V
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935270053512; SC16C750IA44; SC16C750IA44

Philips Semiconductors
9397 750 11623
Product data
6.3 Hardware flow control
6.4 Time-out interrupts
Table 4:
When automatic hardware flow control is enabled, the SC16C750 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, the SC16C750 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the
CTS input returns to a logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C750 will continue to accept data until the receive FIFO is full.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C750 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
Selected trigger level
(characters)
64-byte FIFO
1
16
32
56
Flow control mechanism
Rev. 04 — 20 June 2003
INT pin activation
1
16
32
56
…continued
Negate RTS
16
32
56
60
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UART with 64-byte FIFO
SC16C750
Assert RTS
1
8
16
32
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