SC16C750IA44,512 NXP Semiconductors, SC16C750IA44,512 Datasheet - Page 19

• Manufacturer Part Number: SC16C750IA44,512
• Description: IC UART 64BYTE 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C750IA44,512

• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 2.25 V ~ 5.5 V
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935270053512; SC16C750IA44; SC16C750IA44

Philips Semiconductors
9397 750 11623
Product data
7.3.1 DMA mode
7.3.2 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
Mode 0 (FCR bit 3 = 0):
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1):
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
Table 10:
Bit
7-6
5
4
3
Symbol
FCR[7]
(MSB),
FCR[6]
(LSB)
FCR[5]
FCR[4]
FCR[3]
FIFO Control Register bits description
Rev. 04 — 20 June 2003
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Logic 0 = 16-byte mode (normal default condition).
Logic 1 = 64-byte mode.
Reserved.
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C750 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C750 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Set and enable the interrupt for each single transmit or
Set and enable the interrupt in a block mode operation. The
Table
11.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UART with 64-byte FIFO
SC16C750
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