SC16C750IA44,512 NXP Semiconductors, SC16C750IA44,512 Datasheet - Page 21

• Manufacturer Part Number: SC16C750IA44,512
• Description: IC UART 64BYTE 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C750IA44,512

• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 2.25 V ~ 5.5 V
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935270053512; SC16C750IA44; SC16C750IA44

Philips Semiconductors
9397 750 11623
Product data
7.4 Interrupt Status Register (ISR)
The SC16C750 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12:
Table 13:
Priority
level
1
2
2
3
4
Bit
7-6
5
4
3-1
0
Interrupt source
Interrupt Status Register bits description
ISR[3]
0
0
1
0
0
Symbol
ISR[7-6]
ISR[5]
ISR[4]
ISR[3-1]
ISR[0]
Rev. 04 — 20 June 2003
ISR[2]
1
1
1
0
0
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
64-byte FIFO enable.
Not used.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Logic 0 or cleared = default condition.
Logic 0 = 16-byte operation.
Logic 1 = 64-byte operation.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
ISR[1]
1
0
0
1
0
Table 12 “Interrupt source”
ISR[0]
0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding Register
Empty)
MSR (Modem Status Register)
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UART with 64-byte FIFO
shows the data values
SC16C750
Table
12).
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