DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Clock Circuitry
Table 2–20. Stratix IV GX FPGA Development Board Clock Inputs (Part 2 of 2)
August 2010 Altera Corporation
X7
X8
SMA or X6
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
PCI Express
Edge
Source
Schematic Signal Name
CLKINTOP_100_P
CLKINTOP_100_N
CLKINBOT_100_P
CLKINBOT_100_N
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
CLKINRT_100_P
CLKINRT_100_N
CLKINLT_100_P
CLKINLT_100_N
PCIE_REFCLK_P
PCIE_REFCLK_N
HSMA_CLK_IN0
HSMB_CLK_IN0
CLK_155_P
CLKIN_50
AW22
AN38
AN39
AC34
AV22
AB34
AA35
A21
A20
G38
G39
AC6
AC5
AE5
AB6
AA5
J38
AF6
Pin
W6
W5
G2
G1
LVDS or LVTTL
LVDS or LVTTL
LVDS or LVTTL
LVDS or LVTTL
I/O Standard
2.5-V CMOS
LVPECL
LVTTL
LVTTL
LVDS
LVDS
LVDS
LVDS
HCSL
Stratix IV GX FPGA Development Board Reference Manual
drives the fan-out buffer U50 and LVDS to the
drives the fan-out buffer U50 and LVDS to the
drives the fan-out buffer U50 and LVDS input
drives the fan-out buffer U50 and LVDS input
LVDS input from the installed HSMC cable or
LVDS input from the installed HSMC cable or
LVDS input from the installed HSMC cable or
LVDS input from the installed HSMC cable or
transceiver reference clock input with 100 Ω
Single-ended input from the installed HSMC
Single-ended input from the installed HSMC
board. Can also support two LVTTL inputs.
board. Can also support two LVTTL inputs.
board. Can also support two LVTTL inputs.
board. Can also support two LVTTL inputs.
50 MHz oscillator which drives the global
100 MHz programmable oscillator which
100 MHz programmable oscillator which
100 MHz programmable oscillator which
100 MHz programmable oscillator which
155.52 MHz oscillator which drives the
HCSL input from the PCI Express edge
transceiver QR2 REFCLK input.
transceiver QR2 REFCLK input.
to the top edge PLL input.
to the top edge PLL input.
cable or board.
cable or board.
Description
clock input.
connector.
OCT.
2–23