DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 78

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

A–2
Figure A–1. MAX II CPLD EPM2210 System Controller Block Diagram
Table A–2. Power Rail Measurements that Differ on the Engineering Silicon Board
Stratix IV GX FPGA Development Board Reference Manual
1
7
8
E
Switch
Temperature
Measure
Measure
Results
Results
Power
Blaster
EMB
PC
Schematic Signal Name
S4VCCD_PLL
S4VCCA_GXB
S4VCC_GXB
S4VCC
Figure A–1
whose functionality and external circuit connections on the engineering silicon board
differ from the production silicon board.
silicon MAX II CPLD EPM2210 System Controller block diagram.
Table A–2
engineering silicon board differ from the production silicon board.
page 2–66
The engineering silicon version does not have the programmable oscillator supported
for reference designator X6 but has a fixed frequency 100-MHz oscillator from Epson.
The engineering silicon board version works with the new programmable oscillator if
you remove the Epson device and install it. The latest MAX II CPLD EPM2210 System
Controller also works with older board versions.
Encoder
MAX1619
Controller
Controller
LTC2418
lists information for the targeted power rails whose voltage values on the
shows the production silicon voltage values.
illustrates the Max II CPLD EPM2210 System Controller block diagram
JTAG Control
Virtual-JTAG
SLD-HUB
Voltage (V)
0.95
0.95
3.3
1.2
Calculation
Power
Decoder
Device Pin
VCCD_PLL
VCCL_GXB
VCCHIP
VCCA
VCCR
VCCT
VCC
Figure 2–3 on page 2–7
Information
Register
Control
Register
FPGA core and periphery power
PCI Express hard IP block
PLL digital
XCVR analog TX/RX driver (mA only)
XCVR analog receive
XCVR analog transmit
XCVR clock distribution
PFL
Engineering Silicon Version Differences
MAX II Device
Appendix A: Board Revision History
FSM BUS
Description
August 2010 Altera Corporation
shows the production
Table 2–58 on
GPIO
FLASH
FPGA
SRAM