DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 59

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Memory
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
August 2010 Altera Corporation
U12.F3
U12.G3
U12.D7
U12.C3
U12.C8
U12.C2
U12.A7
U12.A2
U12.B8
U12.A3
U12.D3
U12.C7
U12.B7
U18.E3
U18.F7
U18.F2
U18.F8
U18.H3
U18.H8
U18.G2
U18.H7
U18.E7
U18.F3
U18.G3
U18.D7
U18.C3
U18.C8
U18.C2
U18.A7
U18.A2
U18.B8
U18.A3
U18.D3
U18.C7
U18.B7
U24.E3
U24.F7
U24.F2
Board Reference
Data strobe P byte lane 2
Data strobe N byte lane 2
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Data bus byte lane 3
Write mask byte lane 3
Data strobe P byte lane 3
Data strobe N byte lane 3
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Data bus byte lane 4
Write mask byte lane 4
Data strobe P byte lane 4
Data strobe N byte lane 4
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Data bus byte lane 5
Write mask byte lane 5
Data strobe P byte lane 5
Data strobe N byte lane 5
Data bus byte lane 6
Data bus byte lane 6
Data bus byte lane 6
Description
Schematic Signal
DDR3BOT_DQS_P2
DDR3BOT_DQS_N2
DDR3BOT_DQS_P3
DDR3BOT_DQS_N3
DDR3BOT_DQS_P4
DDR3BOT_DQS_N4
DDR3BOT_DQS_P5
DDR3BOT_DQS_N5
DDR3BOT_DQ24
DDR3BOT_DQ25
DDR3BOT_DQ26
DDR3BOT_DQ27
DDR3BOT_DQ28
DDR3BOT_DQ29
DDR3BOT_DQ30
DDR3BOT_DQ31
DDR3BOT_DQ32
DDR3BOT_DQ33
DDR3BOT_DQ34
DDR3BOT_DQ35
DDR3BOT_DQ36
DDR3BOT_DQ37
DDR3BOT_DQ38
DDR3BOT_DQ39
DDR3BOT_DQ40
DDR3BOT_DQ41
DDR3BOT_DQ42
DDR3BOT_DQ43
DDR3BOT_DQ44
DDR3BOT_DQ45
DDR3BOT_DQ46
DDR3BOT_DQ47
DDR3BOT_DQ48
DDR3BOT_DQ49
DDR3BOT_DQ50
DDR3BOT_DM3
DDR3BOT_DM4
DDR3BOT_DM5
Name
Stratix IV GX FPGA Development Board Reference Manual
1.5-V SSTL Class I
I/O Standard
Stratix IV GX
Pin Number
Device
AM17
AM23
AM22
AW18
AP16
AR16
AH16
AG16
AH17
AG17
AK17
AK16
AU23
AN23
AP23
AR23
AN22
AU24
AR19
AP19
AP18
AN19
AU18
AN18
AU17
AV17
AV26
AU25
AJ16
AL17
AF17
AL16
AT23
AL22
AT24
AT18
AT17
AT25
2–51