DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 39

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Components and Interfaces
Table 2–34. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
August 2010 Altera Corporation
J17.A47
J17.A48
J17.A43
J17.A44
J17.A39
J17.A40
J17.A35
J17.A36
J17.A29
J17.A30
J17.A25
J17.A26
J17.A21
J17.A22
J17.A16
J17.A17
J17.B45
J17.B46
J17.B41
J17.B42
J17.B37
Board Reference
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Figure 2–9
Figure 2–9. PCI Express Reference Clock Levels
The JTAG and SMB are optional signals in the PCI Express specification. Both types of
signals are wired to the Stratix IV GX device but are not required for normal
operation. The PCI Express control DIP switch allows the presence detect grounding
to be altered to enable a ×1, ×4, or ×8 width edge connector. The PCI Express control
DIP switch does not support auto-negotiation.
Express pin assignments. The signal names and directions are relative to the Stratix IV
GX FPGA.
V
V
CROSS MAX
Description
CROSS MIN
shows the PCI Express reference clock levels.
V
V
MAX
MIN
REFCLK –
REFCLK +
= 550 mV
= 250 mV
= 1.15 V
= –0.30 V
Schematic Signal
PCIE_TX_P7
PCIE_TX_N7
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P4
PCIE_TX_N4
PCIE_TX_P3
PCIE_TX_N3
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P0
PCIE_TX_N0
PCIE_RX_P7
PCIE_RX_N7
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P5
Name
Stratix IV GX FPGA Development Board Reference Manual
Table 2–34
I/O Standard
1.4-V PCML
summarizes the PCI
Stratix IV GX
Pin Number
Device
AD36
AD37
AH36
AH37
AB36
AB37
AF36
AF37
AP36
AP37
AT36
AT37
AC38
R38
R39
U38
U39
P36
P37
T36
T37
2–31