ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 31

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

9.2
10. Power Supply
Figure 10-1. Power Supply
4829D–RKE–06/06
Basic Clock Cycle of the Digital Circuitry
N_PWR_ON
(Command via SPI)
PWR_ON
DVCC_OK
VSINT
OFFCMD
XTO_OK
VS1
VS2
The complete timing of the digital circuitry is derived from one clock. According to
page
divider.
T
The clock cycle of the Bit-check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see
is defined in control register 4 (see
by the following formulas for further reference:
BR_Range
f
DCLK
DCLK
• Timing of the polling circuit including bit-check
• TX bit rate
&
29, this clock cycle T
=
controls the following application relevant parameters:
f
---------- -
XTO
16
1
1
S
0
0
1
1
S
R
FF1
R
0
1
0
1
IN
Q
Q
no change
0
1
1
DCLK
3.25V typ.
V_REG1
is derived from the crystal oscillator (XTO) in combination with a
EN
Table 12-16 on page
OUT
BR_Range 0: T
BR_Range 1: T
BR_Range 2: T
BR_Range 3: T
SW_AVCC
SW_DVCC
XDCLK
XDCLK
XDCLK
XDCLK
Table 12-19 on page
40). This clock cycle T
ATA5823/ATA5824
= 8
= 4
= 2
= 1
V_Monitor
(1.6V typ.)
T
T
T
T
DCLK
DCLK
DCLK
DCLK
DVCC_OK
(to XTO and
reset logic)
X
X
X
AVCC
DVCC
X
Lim
Lim
Lim
Lim
41) and X
XDCLK
Figure 9-2 on
is defined
Lim
which
31