ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 59

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Figure 14-8. Receiving Mode (TMODE = 0)
Figure 14-9. Bit Error (TMODE = 0)
4829D–RKE–06/06
Demod_Out
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1'
Bit-check mode
If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data
buffer control logic overwrites the bytes already stored in the TX/RX data buffer. So it is very
important to ensure that the data is read in time so that no buffer overflow occurs in that case
(see
the TX/RX data buffer (see section
ferred to the microcontroller, the counter is decremented, if a byte is received, the counter is
incremented. The counter value is available via the 4-wire serial interface.
An interrupt is issued if the counter while counting forwards reaches the value defined by the
control bits IR0 and IR1 in control register 1.
If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver
is set back to the start-up mode (see
Bit error:
Note:
Writing the control register 1, 4, 5, 6 or 7 during receiving mode resets the TX/RX data buffer
control logic and the counter which indicates the number of received bytes. If the bits OPM0 and
OPM1 are still 1 and OPM2 is still 0 after writing to a control register, the transceiver changes to
the start-up mode (start-up signal processing).
Figure 13-1 on page
Receiving mode
The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus it is not avail-
able via the 4-wire serial interface.
a) t
b) Logical error (no edge detected in the bit center)
'0'
ee
'1'
47). There is a counter that indicates the number of received bytes in
< T
1
1
'0' '0' '0' '0'
1
0
Start-up mode Bit-check mode
Lim_min
1
1
1
0
0
0
“Transceiver Configuration” on page
0
0
Figure 14-1 on page 54
or T
1
0
'0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
Receiving mode
1
0
Byte 16, Byte 32, ...
Byte 15, Byte 31, ...
Byte 14, Byte 30, ...
Byte 13, Byte 29, ...
Byte 12, Byte 28, ...
Byte 11, Byte 27, ...
Byte 10, Byte 26, ...
Byte 9, Byte 25, ...
Byte 8, Byte 24, ...
Byte 7, Byte 23, ...
Byte 6, Byte 22, ...
Byte 5, Byte 21, ...
Byte 4, Byte 20, ...
Byte 3, Byte 19, ...
Byte 2, Byte 18, ...
Byte 1, Byte 17, ...
Lim_max
< t
ee
< T
Lim_min_2T
ATA5823/ATA5824
Receiving mode
and
Figure
or t
ee
> T
14-9).
47). If a byte is trans-
Lim_max_2T
59