ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 45

IC TXRX UHF ASK/FSK 48QFN

ATA5824-PLQW

Manufacturer Part Number
ATA5824-PLQW
Description
IC TXRX UHF ASK/FSK 48QFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5824-PLQW

Frequency
433 ~ 435MHz; 866 ~ 870MHz
Data Rate - Maximum
20kbps
Modulation Or Protocol
ASK, FSK
Applications
RKE, TPM, Security Systems
Power - Output
10dBm
Sensitivity
-116dBm
Voltage - Supply
2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
Current - Receiving
10.5mA
Current - Transmitting
10.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 105°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-

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Manufacturer
Quantity
Price
Part Number:
ATA5824-PLQW
Manufacturer:
ATMEL
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Part Number:
ATA5824-PLQW
Manufacturer:
ATMEL/爱特梅尔
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12.5
4829D–RKE–06/06
Pin PWR_ON
Figure 12-3. Timing Flow Pin N_PWR_ON, Status Bit N_Power_On
To switch the transceiver from OFF to IDLE mode, pin PWR_ON must set to 1 (minimum
0.8
positive edge and switches on DVCC and AVCC.
If V
sets the status bit Power_On to 1, an interrupt is issued (T
pin CLK is available.
If the level on pin PWR_ON was set to 0 before the interrupt is issued, the transceiver stays in
OFF mode.
If the transceiver is in any of the active modes (IDLE, RX, RX_Polling, TX, FD), a positive edge
on pin PWR_ON sets Power_On to 1 (after T
generates an interrupt. If Power_On is still 1 during the positive edge on pin PWR_ON, no inter-
rupt is issued. Power_On and the interrupt is deleted after reading the status register.
DVCC
V
VSINT
exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
) for at least T
Start debounce counter
Stop debounce counter
RX Polling Mode or
N_PWR_ON ?
N_PWR_ON ?
IDLE Mode or
Event on pin
Event on pin
TX Mode or
RX Mode or
FD Mode
T = 0
Y
Y
PWR_ON
(see
N
N
Figure 12-4 on page
Stop debounce counter
N_Power_On = 1;
T = 8195
Pin N_PWR_ON
PWR_ON_IRQ_2
IRQ = 1
= 0 ?
?
Y
Y
T
DCLK
). The state transition Power_On 0
PWR_ON_IRQ_1
N
N
ATA5823/ATA5824
46). The transceiver recognizes the
Stop debounce counter
N_Power_On = 0;
IRQ = 1
) and the output clock on
45
1

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