ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 44

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

12.4
44
Pin N_PWR_ON
ATA5823/ATA5824
(Status register)
To switch the transceiver from OFF to IDLE mode, pin N_PWR_ON must be set to 0 (maximum
0.2
tive edge and switches on DVCC and AVCC.
If V
sets the status bit N_Power_On to 1, an interrupt is issued (T
on pin CLK is available.
If the level on pin N_PWR_ON was set to 1 before the interrupt is issued, the transceiver stays in
OFF mode.
Note:
Figure 12-2. Timing Pin N_PWR_ON, Status Bit N_Power_On
N_POWER_ON
If the transceiver is in any of the active modes (IDLE, TX, RX, RX_Polling, FD), an integrated
debounce logic is active. If there is an event on pin N_PWR_ON, a debounce counter is set to 0
(T = 0) and started. The status is updated, an interrupt is issued and the debounce counter is
stopped after reaching the counter value T = 8195
An event on N_PWR_ON before reaching T = 8195
While the debounce counter is running, the bit CLK_ON in control register 3 is set to 1.
The interrupt is deleted after reading the status register or executes the command Delete_IRQ.
If pin N_PWR_ON is not used, it can be left open because of an internal pull-up resistor (typi-
cally 50 k ).
DVCC, AVCC
N_PWR_ON
DVCC
V
VS2
It is not possible to set the transceiver to OFF-mode by setting pin N_PWR_ON to 1. If pin
N_PWR_ON is not used, it should be left open because of the internal pull-up resistor
exceeds 1.6V (typically) and the XTO is settled, the digital control logic is active and
CLK
IRQ
) for at least T
1.6V (typ)
OFF Mode
N_PWR_ON_IRQ
T
N_PWR_ON_IRQ
(see
IDLE Mode
Figure
12-2). The transceiver recognizes the nega-
T
DCLK
T
DCLK
.
stops the debounce counter.
N_PWR_ON_IRQ
) and the output clock
4829D–RKE–06/06