ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 50

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

13.8
50
4-wire Serial Interface
ATA5823/ATA5824
Table 13-1.
The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Pin CS_POL defines the active level of the CS:
Table 13-2.
When CS is inactive and the transceiver is not in RX transparent mode, SDO_TMDO is in a
high-impedance state.
Pins SCK_POL and SCK_PHA defines the polarity and the phase of the serial clock SCK.
Figure 13-7. Serial Timing SCK_POL = 0, SCK_PHA = 0
SDO_TMDO
Command
Read TX/RX data buffer
Write TX/RX data buffer
Read control/status register
Write control register
OFF command
Delete IRQ
Not used
Not used
SDI_TMDI
CS_POL
0
1
SCK
CS
T
SCK_setup1
X
X can be either V
Command Structure
Active Level of the CS
X
Function
CS active high
CS active low
T
T
T
Setup
CS_setup
Out_enable
iL
MSB
or V
T
Hold
MSB
Bit 7
MSB
iH
0
0
0
0
1
1
1
1
T
Cycle
Bit 6
0
0
1
1
0
0
1
1
T
X
Out_delay
Bit 5
0
1
0
1
0
1
0
1
MSB-1
Bit 4
MSB-1
N4
A4
A4
X
X
X
X
X
Bit 3
X
N3
A3
A3
X
X
X
X
X
LSB
T
Bit 2
SCK_setup2
N2
A2
A2
X
X
X
X
X
X
Bit 1
4829D–RKE–06/06
N1
A1
A1
X
X
X
X
X
T
T
CS_disable
Out_disable
T
X
SCK_hold
Bit 0
LSB
N0
A0
A0
X
X
X
X
X