AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 166
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/39/71/397101/lqfp-128_sml.jpg)
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 166 of 673
- Download datasheet (11Mb)
22.6.2.3
166
SAM7SE512/256/32 Preliminary
Byte Select Access
Figure 22-6. Memory Connection for 2 x 8-bit Data Path Devices
Byte Select Access is used to connect 16-bit devices in a memory page.
Figure 22-7
device type) on NCS2 (BAT = 1).
Figure 22-7. Connection to a 16-bit Data Path Device with Byte and Half-word Access
• The signal A0/NLB is used as NLB and enables the lower byte for both read and write
• The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write
• The signal NWR0/NWE is used as NWE and enables writing for byte or half-word.
• The signal NRD enables reading for byte or half-word.
operations.
operations.
shows how to connect a 16-bit device with byte and half-word access (e.g., SRAM
SMC
SMC
D[15:8]
A[22:1]
D[15:8]
A[19:1]
NWR1
NWR0
D[7:0]
NCS2
D[7:0]
NCS2
NWE
NRD
NRD
NUB
NLB
A0
D[15:8]
D[7:0]
A[18:0]
Write Enable
Read Enable
Memory Enable
A[18:0]
Write Enable
Read Enable
Memory Enable
D[15:8]
A[18:0]
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
D[7:0]
6222F–ATARM–14-Jan-11
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