AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 553
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/39/71/397101/lqfp-128_sml.jpg)
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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37.6.11
Name:
Access:
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
6222F–ATARM–14-Jan-11
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
(
------------------------------------------ -
(
----------------------------------------------------- -
256, 512, or 1024). The resulting period formula will be:
256, 512, or 1024). The resulting period formula will be:
(
------------------------------- -
(
------------------------------------------ -
2
2
X
CRPD
×
×
PWM Channel Period Register
×
MCK
X
CPRD
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
)
×
DIVA
)
30
22
14
)
PWM_CPRDx
6
Read/Write
or
)
(
---------------------------------------------- -
or
CRPD
(
----------------------------------------------------- -
2
×
MCK
×
CPRD
DIVAB
MCK
29
21
13
5
×
DIVB
)
)
28
20
12
4
CPRD
CPRD
CPRD
CPRD
SAM7SE512/256/32 Preliminary
27
19
11
3
26
18
10
2
25
17
9
1
24
16
8
0
553
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