AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 222

FPGA - Field Programmable Gate Array 600K System Gates

AFS600-FGG256

Manufacturer Part Number
AFS600-FGG256
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS600-FGG256

Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
119
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Device Architecture
Table 2-150 • Minimum and Maximum DC Input and Output Levels
Figure 2-127 • AC Loading
Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-152 • HSTL Class II
2- 20 6
HSTL Class II
Drive Strength
15 mA
Note:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Output drive strength is below JEDEC specification.
Input Low (V)
VREF – 0.1
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
DOUT
0.66
0.56
0.49
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output
buffer.
3-9.
Timing Characteristics
Min.
–0.3
V
Input High (V)
3.02
2.57
2.26
t
DP
VREF + 0.1
VREF – 0.1 VREF + 0.1
VIL
Max.
trip
0.04
0.04
0.03
V
t
DIN
. See
Table 2-87 on page 2-168
2.12
1.81
1.59
t
PY
Min.
Measuring Point* (V)
V
Test Point
V
t
EOUT
0.43
0.36
0.32
IH
0.75
HSTL
Class II
Max.
3.6
V
3.08
2.62
2.30
t
R e visio n 1
ZL
VTT
Max.
VOL
0.4
J
V
for a complete table of trip points.
= 70°C, Worst-Case VCC = 1.425 V,
25
20 pF
2.71
2.31
2.03
t
ZH
VREF (typ.) (V)
VCCI – 0.4 15
VOH
Min.
V
0.75
t
LZ
mA mA
I
OL
t
HZ
V
I
15
OH
TT
(typ.) (V)
0.75
t
5.32
4.52
3.97
Max.
mA
I
ZLS
OSL
55
3
Max.
I
mA
4.95
4.21
3.70
OSH
t
66
ZHS
C
Table 3-7 on
3
LOAD
µA
20
I
10
IL
Units
1
(pF)
4
ns
ns
ns
µA
I
10
IH
2
4

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