AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 275

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Combinatorial Cells Dynamic Contribution—P
I/O Input Buffer Dynamic Contribution—P
I/O Output Buffer Dynamic Contribution—P
Standby Mode and Sleep Mode
P
Operating Mode
P
Standby Mode and Sleep Mode
P
Operating Mode
P
Standby Mode and Sleep Mode
P
Operating Mode
P
Standby Mode and Sleep Mode
P
Operating Mode
P
Standby Mode and Sleep Mode
P
S-CELL
C-CELL
C-CELL
NET
NET
INPUTS
INPUTS
OUTPUTS
OUTPUTS
α
F
N
α
F
Routing Net Dynamic Contribution—P
N
N
α
F
N
α
F
N
α
β
F
CLK
CLK
CLK
CLK
CLK
C-CELL
1
S-CELL
C-CELL
1
INPUTS
OUTPUTS
1
1
2
2
= (N
= 0 W
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer enable rate—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
= 0 W
= N
= 0 W
= N
= 0 W
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
S-CELL
= N
= 0 W
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
is the number VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
INPUTS
is the number of I/O input buffers used in the design.
OUTPUTS
is the number of I/O output buffers used in the design.
+ N
* (
* (
C-CELL
α
α
1
* (
2
/ 2) * P
/ 2) * P
α
) * (
2
/ 2) *
α
AC7
AC9
1
/ 2) * P
β
* F
* F
1
CLK
* P
CLK
R e v i s i o n 1
AC8
AC10
NET
* F
INPUTS
* F
CLK
OUTPUTS
CLK
C-CELL
Actel Fusion Family of Mixed Signal FPGAs
Table 3-16 on page
Table 3-16 on page
Table 3-17 on page
Table 3-16 on page
Table 3-16 on page
Table 3-16 on page
3-27.
3-27.
3-27.
3-27.
3-27.
3-27.
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