AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 320

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
5 - 4
Revision
Advance v1.6
(August 2008)
Advance v1.5
(July 2008)
Advance v1.4
(July 2008)
Advance v1.3
(July 2008)
Advance v1.2
(May 2008)
The title of the datasheet changed from Actel Programmable System Chips to Actel
Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip
were changed to mixed signal FPGA.
The references to the Peripherals User’s Guide in the
section
changed to Fusion Handbook.
The following bullet was updated from High-Voltage Input Tolerance: ±12 V to High-
Voltage Input Tolerance: 10.5 V to 12 V.
The following bullet was updated from Programmable 1, 3, 10, 30 µA and 25 mA
Drive Strengths to Programmable 1, 3, 10, 30
This bullet was added to the
section:
ADC Accuracy is Better than 1%
In the
0.72. The following sentence was deleted:
The input range for voltage signals is from –12 V to +12 V with full-scale output
values from 0.125 V to 16 V.
In addition, 2°C was changed to 3°C:
"One analog input in each quad can be connected to an external temperature
monitor diode and achieves detection accuracy of ±3ºC."
The following sentence was deleted:
The input range for voltage signals is from –12 V to +12 V with full-scale output
values from 0.125 V to 16 V.
The title of the datasheet changed from Actel Programmable System Chips to Actel
Fusion Mixed Signal FPGAs. In addition, all instances of programmable system chip
were changed to mixed signal FPGA.
In
references were updated for I
Footnote 3 and 4 were updated and footnote 5 is new.
The
Table 2-25 • Flash Memory Block Timing
The
update. Please review it carefully.
Table 2-45 • ADC Interface Timing
Table 2-56 • Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1),
and AT (x = 3)
The following sentence was deleted from the
The Analog Quad inputs are tolerant up to 12 V + 10%.
The
changed to bottom view. The note below the figure is new.
Table 3-8 · Quiescent Supply Current Characteristics
"ADC Description" section
"V
"180-Pin QFN"
"Integrated Analog Blocks and Analog I/Os"
AREF
and
Analog Reference Voltage"
"Voltage Regulator Power Supply Monitor (VRPSM)" section
was significantly updated.
figure was updated. D1 to D4 are new and the figure was
DC2
was significantly updated. Please review carefully.
"Integrated A/D Converter (ADC) and Analog I/O"
and I
was significantly updated.
R e vi s i o n 1
Changes
DC3
was significantly updated.
.
pin description section was significantly
"Voltage Monitor"
µ
A and 20 mA Drive Strengths.
section, ±4 LSB was changed to
"No-Glitch MUX (NGMUX)"
section:
(IDDQ)1, footnote
were
2-32,
2-102
2-226
2-131
Page
2-110
2-55
2-86
3-11
N/A
N/A
1-4
3-3
I
I
I
2-42