A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet
A54SX32A-PQ208
Specifications of A54SX32A-PQ208
Available stocks
Related parts for A54SX32A-PQ208
A54SX32A-PQ208 Summary of contents
Page 1
... V Input Tolerance and 5 V Drive Strength • Very Low Power Consumption • Deterministic, User-Controllable Timing • Unique In-System Diagnostic Capability with Silicon Explorer II • Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) A54SX32A A54SX72A 32,000 48,000 2,880 1,800 1,080 1,980 228 3 0 Yes Yes 5 ...
Page 2
... HiRel SX-A Family FPGAs Ordering Information A54SX32A – 1 Speed Grade Part Number A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Figure 1 • HiRel SX-A Family Ordering Information Ceramic Device Resources Device A54SX32A A54SX72A Note: Package Definitions: CQFP = Ceramic Quad Flat Pack ...
Page 3
... Orientation Only 1 1014 2009 In accordance with applicable Actel device specification 1015, Condition D, 160 hours @ 125° hours @ 150°C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 2009 v2 ...
Page 4
HiRel SX-A Family FPGAs Table of Contents General Description QML Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
... Routing Tracks Tungsten Plug Contact Note: HiRel A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. HiRel A54SX32A has three layers of metal with antifuse between Metal 2 and Metal 3. Figure 1-1 • HiRel SX-A Family Interconnect Elements ...
Page 6
... Module Organization Actel has arranged all C-cell and R-cell logic modules into horizontal banks called clusters. There are two type of clusters: Type 1 clusters contain two C-cells and one R-cell, and Type 2 clusters contain one C-cell and two CLRB R-cells ...
Page 7
... The Actel segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays ...
Page 8
HiRel SX-A Family FPGAs Type 1 SuperClusters Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters Type 2 SuperClusters Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters 1 -4 Direct Connect • No Antifuses • 0.1 ns ...
Page 9
... LOW or HIGH on the board. They must not be left floating, except in HiRel A54SX72A, where they can be configured as regular I/Os. Figure 1-8 and CLKB circuit used in HiRel A54SX32A. CLKBUF CLKBUFI CLKINT CLKINTI Note: This does not include the clock pad for HiRel A54SX72A. ...
Page 10
... I known state during power-up. Just slightly before V disabled so the I/Os will behave normally. For more information about the power-up resistors, see the Actel application note Swap and Cold-Sparing Table 1-3 for more information on I/O features. ...
Page 11
... Table 1-4 • Power-Up Time at which I/Os Become Active Ramp Rate 0.25 V/µs 0.025 V/µs Units µs HiRel A54SX32A 10 HiRel A54SX72A 10 Power Requirements The HiRel SX-A family supports 2.5 V/3.3 V/5 V mixed- voltage operation and is designed to tolerate 5 V inputs for all standards except 3.3 V PCI. In PCI mode, I/Os support 3 ...
Page 12
... BST pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set to logical HIGH. Development Tool Support HiRel SX-A devices are fully supported by the Actel line of FPGA development tools, including the Actel Designer ® software ...
Page 13
... Related Documents Application Notes Global Clock Networks in Actel Antifuse Devices www.actel.com/documents/GlobalClk_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications www.actel.com/documents/HotSwapColdSparing_AN.pdf Datasheets SX-A Family FPGAs www.actel.com/documents/SXA_DS.pdf v2.0 HiRel SX-A Family FPGAs 1-9 ...
Page 14
HiRel SX-A Family FPGAs Detailed Specifications 2.5 V/3.3 V/5 V Operating Conditions Table 1-6 • Absolute Maximum Ratings Symbol V DC Supply Voltage CCI Supply Voltage CCA V DC Supply Voltage CCA Output ...
Page 15
... For AC signals, the input signal may undershoot during transitions to –1.2 V for no longer than 11 ns. Current during the transition must not exceed 95 mA. 2. For AC signals, the input signal may overshoot during transitions to V transition must not exceed 95 mA. 3. The IBIS model can be found at www.actel.com/techdocs/models/ibis.html. 4. See the SX-A Family FPGAs datasheet for more information on commercial devices. ...
Page 16
HiRel SX-A Family FPGAs 5 V PCI Compliance for the HiRel SX-A Family The HiRel SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-10 • DC Specifications, ...
Page 17
Table 1-11 • AC Specifications PCI Operation Symbol Parameter I Switching OH(AC) Current High (Test Point) I Switching OL(AC) Current Low (Test Point) I Low Clamp Current CL slew Output Rise Slew Rate R slew Output Fall Slew ...
Page 18
HiRel SX-A Family FPGAs 3.3 V PCI Compliance for the HiRel SX-A Family The HiRel SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-12 • DC Specifications, ...
Page 19
Table 1-13 • AC Specifications, 3.3 V PCI Operation Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current Low OL(AC) (Test Point) I Low Clamp Current CL I High Clamp Current CH slew Output Rise Slew Rate ...
Page 20
... Table air flow rates. θ Pin Count jc 84 – 208 6.3 256 6 – θ (°C/W) ja Software Tools section on the Actel v2 Table 1-14. are given for two different ja θ θ Still Air 300 ft/min ja ja – – 150° ...
Page 21
HiRel SX-A Timing Model Input Delays I/O Module t = 1.0 ns INYH t RCKH (100% Load) Routed Clock I/O Module t = 1.0 ns INYH t HCKL Hardwired Clock Note: *Values shown for are HiRel A54SX72A–1, worst-case military conditions ...
Page 22
HiRel SX-A Family FPGAs V CC GND D 50% 50 1.5 V PAD 1 DLH DHL Figure 1-16 • Output Buffer Delays Load 1 (for propagation delays) From Output Under Test 35 pF ...
Page 23
D t SUD CLK Q CLR PRESET Figure 1-20 • Cell Timing Characteristics PRESET D Q CLK CLR (Positive Edge Triggered HPWH' t RPWH t HPWL' t RPWL t RCO t CLR t WASYN v2.0 HiRel SX-A ...
Page 24
HiRel SX-A Family FPGAs Timing Characteristics Timing characteristics for HiRel SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all HiRel SX-A family members. Internal routing delays are device-dependent. Design ...
Page 25
... Table 1-16 • HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, V Parameter 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, DirectConnect Routing Delay, FastConnect Routing Delay RD1 Routing Delay RD2 Routing Delay RD3 Routing Delay RD4 Routing Delay ...
Page 26
... HiRel SX-A Family FPGAs Table 1-17 • HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, V Parameter Dedicated (hardwired) Array Clock Network t Input Low to High (pad to R-Cell input) HCKH t Input High to Low (pad to R-Cell input) HCKL t Minimum Pulse Width High HPWH t Minimum Pulse Width Low ...
Page 27
... Table 1-18 • HiRel A54SX32A Timing Characteristics Worst-Case Military Conditions, V Parameter Dedicated (hardwired) Array Clock Network t Input Low to High (pad to R-Cell input) HCKH t Input High to Low (pad to R-Cell input) HCKL t Minimum Pulse Width High HPWH t Minimum Pulse Width Low HPWL t Maximum Skew ...
Page 28
... HiRel SX-A Family FPGAs Table 1-19 • A54SX32A Timing Characteristics (Worst-Case Military Conditions V Parameter Description 1 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ENHZ 2 d Delta Low to High TLH ...
Page 29
... Table 1-20 • A54SX32A Timing Characteristics (Worst-Case Military Conditions V Parameter Description 1 5.0 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ENHZ 2 d Delta Low to High TLH 2 d Delta High to Low THL 5 ...
Page 30
HiRel SX-A Family FPGAs Table 1-21 • HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, V Parameter 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, DirectConnect ...
Page 31
Table 1-22 • HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, V Parameter Dedicated (hardwired) Array Clock Network t Input Low to High (pad to R-Cell input) HCKH t Input High to Low (pad to R-Cell input) HCKL t Minimum Pulse ...
Page 32
HiRel SX-A Family FPGAs Table 1-23 • HiRel A54SX72A Timing Characteristics Worst-Case Military Conditions, V Parameter Dedicated (hardwired) Array Clock Network t Input Low to High (pad to R-Cell input) HCKH t Input High to Low (pad to R-Cell input) ...
Page 33
Table 1-24 • A54SX72A Timing Characteristics (Worst-Case Military Conditions V Parameter Description 1 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...
Page 34
HiRel SX-A Family FPGAs Table 1-25 • A54SX72A Timing Characteristics (Worst-Case Military Conditions V Parameter Description 1 5.0 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ...
Page 35
Pin Description CLKA/B Clock A/B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, 3.3 V PCI PCI specifications. The clock input is buffered prior to clocking the R-cells. ...
Page 36
... The TRST pin is equipped with an internal pull- up resistor. This pin functions as an I/O when the Reserve JTAG Test Reset Pin check box is cleared in the Actel Designer software. V CCI Supply voltage for I/Os. See V power pins in the device should be connected ...
Page 37
... Package Pin Assignments 84-Pin CQFP Pin #1 Index Figure 2-1 • 208-Pin CQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html 84-Pin CQFP v2.0 HiRel SX-A Family FPGAs 2-1 ...
Page 38
... V CCA 58 GND 59 I CCA 61 GND 62 I/O 63 I/O 64 I/O 65 I/O 66 I CCI 69 GND 70 I/O v2.0 84-Pin CQFP HiRel A54SX32A Pin Number Function 71 I/O 72 CLKA 73 CLKB 74 PRA, I/O 75 I/O 76 I/O 77 I/O 78 GND 79 V CCA 80 I/O 81 I/O 82 TCK, I/O 83 TDI, I/O 84 I/O ...
Page 39
... Figure 2-2 • 208-Pin CQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html. 164 163 162 161 160 159 158 157 208-Pin CQFP 100 101 102 103 104 v2.0 HiRel SX-A Family FPGAs 156 ...
Page 40
... I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O QCLKA v2.0 208-Pin CQFP HiRel HiRel Pin A54SX32A A54SX72A Number Function Function 75 I/O I/O 76 PRB, I/O PRB, I/O 77 GND GND CCA CCA 79 GND GND I/O I/O ...
Page 41
... NC NC 183 GND GND 184 V V CCA CCA 185 GND GND v2.0 HiRel SX-A Family FPGAs 208-Pin CQFP HiRel HiRel Pin A54SX32A A54SX72A Number Function Function 186 PRA, I/O PRA, I/O 187 I/O V CCI 188 I/O I/O 189 I/O I/O 190 ...
Page 42
... Figure 2-3 • 256-Pin CQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource Center at www.actel.com/products/rescenter/package/index.html 200 199 198 197 196 195 194 193 256-Pin CQFP 121 122 123 124 125 126 127 128 v2.0 192 191 ...
Page 43
... I/O I/O 70 I/O I/O 71 I/O I/O 72 I/O I/O 73 I/O V CCI 74 I/O I/O v2.0 HiRel SX-A Family FPGAs 256-Pin CQFP HiRel HiRel Pin A54SX32A A54SX72A Number Function Function 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O ...
Page 44
... I/O I/O 182 I/O I/O 183 I/O V CCI 184 I/O I/O 185 I/O I/O v2.0 256-Pin CQFP HiRel HiRel Pin A54SX32A A54SX72A Number Function Function 186 I/O I/O 187 I/O I/O 188 I/O I/O 189 GND GND 190 I/O I/O 191 ...
Page 45
... I/O 242 I/O I/O 243 I/O I/O 244 I/O I/O 245 I/O I/O v2.0 HiRel SX-A Family FPGAs 256-Pin CQFP HiRel HiRel Pin A54SX32A A54SX72A Number Function Function 246 I/O I/O 247 I/O I/O 248 I/O I/O 249 I/O V CCI 250 ...
Page 46
...
Page 47
Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version—v2.0 Advanced v1.2 The 84-pin CQFP package information was added to the datasheet. (December ...
Page 48
... Description" section The “Package Characteristics and Mechanical Drawings” section has been eliminated from the datasheet. The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical Drawings,” available on the Actel web site was updated. was updated. ...
Page 49
Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: ...
Page 50
... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court, Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 USA Camberley, Surrey GU17 9AB United Kingdom Phone 650 ...