A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 32

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-23 • HiRel A54SX72A Timing Characteristics
1 -2 8
Parameter
Dedicated (hardwired) Array Clock Network
t
t
t
t
t
t
f
Routed Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
Quadrant Array Clock Networks
t
t
t
t
t
t
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating
HCKH
HCKL
HPWH
HPWL
HCKSW
HP
HMAX
RCKH
RCKL
RCKH
RCKL
RCKH
RCKL
RPWH
RPWL
RCKSW
RCKSW
RCKSW
QCKH
QCHKL
QCKH
QCHKL
QCKH
QCHKL
QPWH
QPWL
QCKSW
QCKSW
QCKSW
HiRel SX-A Family FPGAs
device performance. Post-route timing analysis or simulation is required to determine actual performance.
Worst-Case Military Conditions, V
Input Low to High (pad to R-Cell input)
Input High to Low (pad to R-Cell input)
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
Minimum Period
Maximum Frequency
Input Low to High (pad to R-Cell input, light load)
Input High to Low (pad to R-Cell input, light load)
Input Low to High (pad to R-Cell input, 50% load)
Input High to Low (pad to R-Cell input, 50% load)
Input Low to High (pad to R-Cell input, 100% load)
Input High to Low (pad to R-Cell input, 100% load)
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (light load)
Maximum Skew (50% load)
Maximum Skew (100% load)
Input Low to High (Light Load)
(Pad to R-cell Input)
Input High to Low (Light Load)
(Pad to R-cell Input)
Input Low to High (50% Load)
(Pad to R-cell Input)
Input High to Low (50% Load)
(Pad to R-cell Input)
Input Low to High (100% Load)
(Pad to R-cell Input)
Input High to Low (100% Load)
(Pad to R-cell Input)
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
PD
+ t
RD1
Description
+ t
PDn
, t
CCA
RCO
= 2.25 V, V
+ t
RD1
+ t
v2.0
PDn
CCI
, or t
= 4.75 V, T
PD1
+ t
Min.
2.2
2.2
2.2
2.2
4.4
2.2
2.2
RD1
J
'–1' Speed
= 125°C
+ t
SUD
Max.
, whichever is appropriate.
227
2.4
2.2
2.1
3.5
3.8
3.7
4.1
3.9
4.3
3.3
3.4
3.6
1.9
1.7
2.2
2.0
2.5
2.3
1.3
1.5
1.7
Min.
2.6
2.6
5.2
2.6
2.6
2.6
2.6
'Std' Speed
Max.
192
2.8
2.6
2.4
4.1
4.5
4.4
4.8
4.6
5.1
3.9
4.0
4.2
2.2
2.0
2.6
2.3
2.9
2.6
1.5
1.8
2.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns