A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 17

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-11 • AC Specifications, 5 V PCI Operation
Figure 1-12 • 5 V PCI Slew Load
Symbol
I
I
I
slew
slew
Notes:
1. Refer to the V/I curves in
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point, rather than
3. Maximum current requirements must be met as drivers pull beyond the last step voltage.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
OH(AC)
OL(AC)
CL
I
for V
OH
half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and
RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, or INTD#,
which are open drain outputs.
toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
The equation defined maximum should be met by the design. In order to facilitate component testing, a maximum current test
point is defined for each side of the output driver.
point within the transition range. The specified load
with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not
required prior to revision 2.1 of the specification, there may be components on the market for some time yet that have faster edge
rates. Therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and
they should ensure that signal integrity modeling accounts for this. Rise in slew rate does not apply to open drain outputs.
R
F
= 11.9 * (V
CCI
> V
Switching
Current High
(Test Point)
Switching
Current Low
(Test Point)
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
OUT
OUT
> 3.1 V
Parameter
– 5.25) * (V
Figure 1-11 on page
OUT
Output
Buffer
+ 2.45)
3.1 < V
1.4 ≤ V
0.71 > V
0.4 V – 2.4 V load
2.4 V – 0.4 V load
2.2 > V
0 < V
V
–5 < V
V
V
Condition
1-12. Switching current characteristics for REQ# and GNT# are permitted to be one-
OUT
OUT
OUT
OUT
OUT
OUT
Pin
OUT
OUT
= 0.71
1 kΩ
= 3.1
≥ 2.2
IN
< V
(Figure
≤ 1.4
< 2.4
> 0.55
EQ 1-1
≤ –1
> 0
CCI
3
1
3
1, 3
1, 2
1
1, 3
1-12) is optional; i.e., the designer may elect to meet this parameter
1
4
4
v2.0
½" Maximum
10 pF
(–44 + (V
I
for 0 V < V
OL
–25 + (V
= 78.5 * V
V
OUT
OUT
Min.
1 kΩ
IN
–44
95
OUT
/0.023
1
1
+ 1)/0.015
– 1.4)/0.024
OUT *
< 0.71 V
V
EQ 1-1
CC
(4.4 – V
and
EQ 1-1 on page 1-13
EQ 1-2 on page 1-13
OUT
EQ 1-2
)
HiRel SX-A Family FPGAs
Max.
–142
206
5
5
define these maxima.
Units
V/ns
V/ns
mA
mA
mA
mA
mA
mA
mA
EQ 1-2
1-13