A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 25

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-16 • HiRel A54SX32A Timing Characteristics
Parameter
C-Cell Propagation Delays
t
Predicted Routing Delays
t
t
t
t
t
t
t
t
R-Cell Timing
t
t
t
t
t
t
t
t
t
Input Module Propagation Delays
t
t
t
t
t
t
t
t
Input Module Predicted Routing Delays2
t
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs under worst-case operating conditions. These parameters should be used for estimating
PD
DC
FC
RD1
RD2
RD3
RD4
RD8
RD12
RCO
CLR
PRESET
SUD
HD
WASYN
RECASYN
HASYN
MPW
INYH
INYL
INYH
INYL
INYH
INYL
INYH
INYL
IRD1
IRD2
IRD3
IRD4
IRD8
IRD12
device performance. Post-route timing analysis or simulation is required to determine actual performance.
Worst-Case Military Conditions, V
Internal Array Module
FO = 1 Routing Delay, DirectConnect
FO = 1 Routing Delay, FastConnect
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
Sequential Clock to Q
Asynchronous Clear to Q
Asynchronous Preset to Q
Flip-Flop Data Input Setup
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery
Asynchronous Hold Time
Clock Pulse Width
Input Data Pad to Y HIGH 3.3 V PCI
Input Data Pad to Y LOW 3.3 V PCI
Input Data Pad to Y HIGH 3.3 V LVTTL
Input Data Pad to Y LOW 3.3 V LVTTL
Input Data Pad to Y HIGH 5 V PCI
Input Data Pad to Y LOW 5 V PCI
Input Data Pad to Y HIGH 5 V TTL
Input Data Pad to Y LOW 5 V TTL
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
2
1
PD
+ t
RD1
Description
+ t
PDn
, t
CCA
RCO
= 2.25 V, V
+ t
RD1
+ t
v2.0
PDn
CCI
, or t
= 3.0 V, T
PD1
+ t
Min.
0.8
0.0
J
1.7
2.0
RD1
'–1' Speed
= 125°C
+ t
SUD
Max.
, whichever is appropriate.
1.2
0.1
0.2
0.5
0.7
0.9
1.2
2.9
0.9
0.7
0.8
0.7
0.7
0.8
0.8
2.3
1.1
1.1
1.3
2.2
1.3
0.5
0.7
0.9
1.2
2.9
2
2
Min.
1.0
0.0
2.0
2.3
'Std' Speed
HiRel SX-A Family FPGAs
Max.
1.4
0.1
0.2
0.6
0.8
1.3
2.4
3.5
1.1
0.8
0.9
0.9
0.9
0.9
1.0
2.7
1.3
1.2
1.5
2.6
1.5
0.6
0.8
1.3
2.4
3.5
1
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-21