A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 7

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Type 2 SuperCluster is a two-wide group containing one
Type 1 cluster and one Type 2 cluster. HiRel SX-A devices
feature more Type 1 SuperCluster modules than Type 2
SuperCluster modules because designers typically require
significantly more combinatorial logic than flip-flops.
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
clusters and SuperClusters
Figure 1-6 on page
dramatically reduces the number of antifuses required to
complete a circuit, ensuring the highest possible
performance.
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring
R-cell in a given SuperCluster. DirectConnect uses a
Figure 1-4 •
Internal Logic
Connect
Direct
CLKA,
Input
CLKB,
HCLK
Cluster 1
Cluster Organization
CKS
S0
Data Input
1-4). This routing architecture also
Type 1 SuperCluster
Routed
R-Cell
(Figure 1-5 on page 1-4
CKP
S1
D
Cluster 2
PSETB
CLRB
Q
Y
and
v2.0
hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a single SuperCluster and
vertical routing to the SuperCluster immediately below
it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. The Actel segmented routing structure provides
a variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100 percent automatic place-and-route software to
minimize signal propagation delays.
D0
D1
D2
D3
DB
Cluster 2
Type 2 SuperCluster
A0
C-Cell
B0
Sa
HiRel SX-A Family FPGAs
Cluster 1
A1
B1
Sb
Y
1-3