A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 19

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-13 • AC Specifications, 3.3 V PCI Operation
Figure 1-14 • 3.3 V PCI Slew Load
Symbol
I
I
I
I
slew
slew
Notes:
1. Refer to the V-I curves in
2. Maximum current requirements must be met as drivers pull beyond the last step voltage.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
OH(AC)
OL(AC)
CL
CH
I
for V
OH
half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and
RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, or INTD#,
which are open drain outputs.
The equation-defined maximum should be met by the design. To facilitate component testing, a maximum current test point is
defined for each side of the output driver.
point within the transition range. The specified load
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
R
F
= (98.0/V
CCI
> V
Switching Current High
(Test Point)
Switching Current Low
(Test Point)
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
OUT
CCI
) * (V
> 0.7V
Parameter
OUT
CCI
Figure 1-13 on page
– V
CCI
) * (V
Output
Buffer
OUT
0.3V
0.6V
0.7V
V
0.2V
0.6V
+ 0.4V
0.18V
V
CCI
CCI
0 < V
CCI
CCI
V
CCI
1-14. Switching current characteristics for REQ# and GNT# are permitted to be one-
V
+ 4 > V
CCI
CCI
OUT
> V
OUT
–3 < V
CCI
Condition
≤ V
> V
Pin
CCI
OUT
< V
to 0.6V
to 0.2V
1 kΩ
OUT
= 0.18V
= 0.7V
> V
)
OUT
OUT
OUT
(Figure
≤ 0.3V
EQ 1-3
IN
IN
≥ 0.6V
OUT
< 0.9V
> 0.1V
≤ –1
≥ V
< V
CCI
CCI
CC
CC
> 0
CCI
CCI
1-14) is optional; i.e., the designer may elect to meet this parameter
CCI
v2.0
load
load
2
CCI
2
½" Maximum
CCI
CCI
1, 2
+ 1
1
1, 2
10 pF
1
3
3
1
1
I
for 0 V < V
OL
= (256/V
25 + (V
–17.1 + (V
–25 + (V
1 kΩ
OUT
IN
CCI
26.7V
–12V
– V
16V
Min.
IN
) * V
< 0.18V
1
1
CCI
CCI
+ 1)/0.015
CCI
V
CCI
OUT
EQ 1-3
CC
OUT
– 1)/0.015
– V
OUT
CC
* (V
and
)
CCI
EQ 1-4
– V
HiRel SX-A Family FPGAs
OUT
–32V
38V
EQ 1-3
EQ 1-4
Max.
define these maxima.
)
4
4
CCI
CCI
Units
V/ns
V/ns
mA
mA
mA
mA
mA
mA
mA
mA
EQ 1-4
1-15