A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 12

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Flexible Mode
When the Reserve JTAG box is not selected, the HiRel
SX-A device is placed in flexible mode, which allows the
TDI, TCK, and TDO pins to function as user I/Os or BST
pins. In this mode, the internal pull-up resistors on the
TMS and TDI pins are disabled. An external 10 kΩ pull-up
resistor to V
The TDI, TCK, and TDO pins are transformed from user
I/Os to BST pins when a rising edge on TCK is detected
while TMS is at logical LOW. Once the BST pins are in test
mode, they will remain in BST mode until the internal
BST state machine reaches the "logic reset" state. At this
point the BST pins will be released and will function as
regular I/O pins. The "logic reset" state is reached five
TCK cycles after the TMS pin is set to logical HIGH.
Development Tool Support
HiRel SX-A devices are fully supported by the Actel line
of FPGA development tools, including the Actel Designer
software
Environment (IDE). Designer software, the Actel suite of
FPGA development tools for PCs and Workstations,
includes the ACTgen Macro Builder, timing-driven place-
and-route, timing analysis tools, and fuse file generation.
Libero IDE is a design management environment that
integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero IDE includes
Figure 1-10 • Probe Setup
1 -8
HiRel SX-A Family FPGAs
and
CCI
is required on the TMS pin.
Actel
Serial Connection
Libero
®
Integrated
Silicon Explorer II
Design
16
Additional
Channels
v2.0
Synplify
ModelSim
Silicon Explorer II.
HiRel SX-A Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to
the PRA/PRB pins for observation.
the interconnection between Silicon Explorer II and the
FPGA when performing in-circuit verification. The TRST
pin is equipped with an internal pull-up resistor from the
reset state during probing. It is recommended that TRST
be left floating.
Design Considerations
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as
input or bidirectional ports. Since these pins are active
during probing, critical input signals through these pins
are not available. In addition, do not program the
Security Fuse, as this disables the Probe Circuit. Actel
recommends that you use a series 70 Ω termination
resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, and PRB). The 70 Ω termination is used to prevent
data transmission corruption during probing and
reading back the checksum.
TMS
TCK
TDI
70 Ω
70 Ω
70 Ω
®
, ViewDraw
®
HDL Simulator, WaveFormer Lite
70 Ω
70 Ω
70 Ω
TDO
PRA
PRB
®
, the Actel Designer software,
HiRel SX-A FPGA
Figure 1-10
™
, and Actel
illustrates