FAN7393M Fairchild Semiconductor, FAN7393M Datasheet - Page 15

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FAN7393M

Manufacturer Part Number
FAN7393M
Description
IC GATE DVR HALF BRIDGE 14-SOIC
Manufacturer
Fairchild Semiconductor
Type
Half-Bridge Gate Drive ICr
Datasheet

Specifications of FAN7393M

Configuration
Half Bridge
Input Type
Non-Inverting
Delay Time
550ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
600V
Voltage - Supply
10 V ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (0.154", 3.90mm Width)
Product
Half-Bridge Drivers
Rise Time
40 ns
Fall Time
20 ns
Propagation Delay Time
550 ns
Supply Voltage (max)
20 V
Supply Voltage (min)
10 V
Supply Current
0.9 mA
Maximum Power Dissipation
1 W
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FAN7393 • Rev. 1.0.0
© 2009 Fairchild Semiconductor Corporation
Application Information
Negative V
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest diffi-
culty with this circuit is the negative voltage present at
the emitter of the high-side switching device when the
high-side switch is turned off in half-bridge applications.
If the high-side switch, Q1, turns-off while the load cur-
rent is flowing to an inductive load; a current commuta-
tion occurs from high-side switch, Q1, to the diode, D2,
in parallel with the low-side switch of the same inverter
leg. Then the negative voltage present at the emitter of
the high-side switching device, just before the freewheel-
ing diode, D2, starts clamping, causes load current to
suddenly flow to the low-side freewheeling diode, D2, as
shown in Figure 44.
This negative voltage can be trouble for the gate driver’s
output stage. There is the possibility to develop an over-
voltage condition of the bootstrap capacitor, input signal
missing, and latch-up problems because it directly
affects the source V
Figure 45. This undershoot voltage is called “negative V
transient.
Figure 45. V
Figure 44. Half-Bridge Application Circuits
GND
V
Q1
GND
DC+ Bus
S
S
Transient
S
Q1
V
Q3
Waveforms During Q1 Turn-Off
S1
S
pin of the gate driver, as shown in
D1
D3
i
i
LOAD
freewheeling
Load
Freewheeling
D2
D4
V
Q2
Q4
S2
S
15
Figure 46 and Figure 47 show the commutation of the
load current between the high-side switch, Q1, and low-
side freewheelling diode, D3, in same inverter leg. The
parasitic inductances in the inverter circuit from the die
wire bonding to the PCB tracks are jumped together in
L
and low-side switch, Q4, are turned on, the V
below DC+ voltage by the voltage drops associated with
the power switch and the parasitic inductances of the cir-
cuit due to load current is flows from Q1 and Q4, as
shown in Figure 46. When the high-side switch, Q1, is
turned off and Q4, remained turned on, the load current
to flows the low-side freewheeling diode, D3, due to the
inductive load connected to V
The current flows from ground (which is connected to the
COM pin of the gate driver) to the load and the negative
voltage present at the emitter of the high-side switching
device.
In this case, the COM pin of the gate driver is at a higher
potential than the V
ated with freewheeling diode, D3, and parasitic ele-
ments, L
C
and L
Figure 47. Q1 Turn-Off and D3 Conducting
C3
E
for each IGBT. When the high-side switch, Q1,
and L
Figure 46. Q1 and Q4 Turn-On
DC+ Bus
DC+ Bus
E3
S
.
L
Q1
V
Q3
L
L
L
L
Q1
L
V
Q3
L
L
C1
E1
S1
pin due to the voltage drops associ-
C3
E3
C1
E1
S1
C3
E3
V
V
V
V
LC3
LE3
LC1
LE1
D1
D3
D1
D3
i
i
S1
i
i
LOAD
freewheeling
LOAD
freewheeling
, as shown in Figure 47.
Load
Load
www.fairchildsemi.com
D2
D4
D2
D4
V
V
V
V
S1
LC4
LE4
LC4
LE4
node is
L
L
V
L
Q2
L
Q4
L
L
V
L
L
Q2
Q4
C2
E2
C4
C2
E2
S2
E4
C4
E4
S2

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