FAN7393MX Fairchild Semiconductor, FAN7393MX Datasheet
FAN7393MX
Specifications of FAN7393MX
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FAN7393MX Summary of contents
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... Motor Drive Inverter Ordering Information Part Number FAN7393M 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 FAN7393MX Inch Narrow Body, 225SOP For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 Description ...
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... Typical Application Diagrams +15V PWM PWM IC Shutdown Control Internal Block Diagram IN 1 250K SCHMITT 5V TRIGGER INPUT 250K 2 SD SHOOT THOUGH PREVENTION R DTINT DT 4 DEAD-TIME { DTMIN=370ns } Pin and 14 are no connection © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0 BOOT BOOT FAN7393 ...
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... COM © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0 COM Figure 3. Pin Configurations (Top View) Description Logic Input for High-Side and Low-Side Gate Driver Output, In-Phase with HO Logic Input for Shutdown Logic Ground Dead-Time Control with External Resistor (Referenced to V Ground ...
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... Logic Input Voltage (SD Programmable Dead-Time Pin Voltage V Logic Ground SS T Operating Ambient Temperature A Note: 4. Shutdown (SD) input is internally clamped with 5.2V. © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 =25°C unless otherwise specified. A Characteristics ( under any circumstances. Parameter (4) 4 Min. Max. Unit -0 ...
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... Output Low, Short-Circuit Pulsed Current O- Allowable Negative Propagation to HO Note: 5 These parameters guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 and T = 25°C, unless otherwise specified. The /COM and are applicable to the respective input leads: IN and SD. The V Test Condition V ...
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... Turn-Off Fall Time F Dead Time: LO Turn-Off to HO Turn-On & Turn-Off to LO Turn-On MDT Dead Time matching=|DT Note: 6 The turn-on propagation delay time includes dead time. © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 =1000pF, DT=V and T =25°C, unless otherwise specified Conditions (6) ...
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... Figure 6. Turn-On Rise Time vs. Temperature 550 500 450 400 350 300 250 -40 - Temperature [°C] Figure 8. Dead Time (R =0Ω) vs. Temperature DT © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 400 350 300 250 200 150 100 High-Side 50 Low-Side 100 120 -40 -20 Figure 5 ...
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... Figure 12. Delay Matching vs. Temperature 270 250 230 210 190 170 150 130 110 90 -40 - Temperature [°C] Figure 14. Shutdown Propagation Delay vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 (Continued) 250 DT1 DT2 200 Ω R =750K DT 150 100 100 120 ...
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... Temperature [°C] Figure 18. Operating V DD vs. Temperature 10.0 9.5 9.0 8.5 8.0 -40 - Temperature [°C] Figure 20. V UVLO+ vs. Temperature DD © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 (Continued) 100 - 100 120 Supply Current Figure 17. Quiescent V 800 600 400 200 0 - 100 ...
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... Temperature [°C] Figure 24. High-Level Output Voltage vs. Temperature 3.0 2.5 2.0 1.5 1.0 -40 - Temperature [°C] Figure 26. Logic High Input Voltage vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 (Continued) 9.5 9.0 8.5 8.0 7.5 - 100 120 Figure 23. V 1.0 High-Side ...
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... Supply Voltage [V] Figure 30. Turn-On Propagation Delay vs. Supply Voltage Supply Voltage [V] Figure 32. Turn-On Rise Time vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 (Continued -10 -11 -12 - 100 120 -40 Figure 29. Allowable Negative V 400 350 300 250 200 150 ...
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... Supply Voltage [V] Figure 34. Quiescent V DD vs. Supply Voltage 2.0 1.5 1.0 0.5 0 Supply Voltage [V] Figure 36. High-Level Output Voltage vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 (Continued) 100 Supply Current Figure 35. Quiescent V 1.0 High-Side 0.8 Low-Side 0.6 ...
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... Switching Time Definitions SD LO +15V μ DT1 DT2 IN 50 OFF F 90 © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0 COM 1nF 100nF Figure 38. Switching Time Test Circuit Shutdown DT2 DT1 DT2 Figure 39. Input/Output Timing Diagram 10 90% 10% Figure 40. Switching Time Waveform Definition ...
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... SD IN 50% t OFF 90 IN(LO) 50% 50% IN(HO 10% © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0 Figure 41. Shutdown Waveform Definition LO-HO 10% MDT LO-HO HO-LO Figure 42. Dead Time Waveform Definition LO HO 10% Figure 43. Delay Matching Waveform Definition 14 50% DT HO-LO 10% 90% t OFF 50% 50% MT OFF ...
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... S GND Figure 45. V Waveforms During Q1 Turn-Off S © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 Figure 46 and Figure 47 show the commutation of the load current between the high-side switch, Q1, and low- side freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die ...
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... To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. © 2009 Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 transient performance Placement of Components S The recommended selection of component is as follows: Place a bypass capacitor between the V pins. A ceramic 1µ ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FAN7393 • Rev. 1.0.0 18 www.fairchildsemi.com ...