IDTTSE2002B3CNCG8 IDT, Integrated Device Technology Inc, IDTTSE2002B3CNCG8 Datasheet - Page 11
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IDTTSE2002B3CNCG8
Manufacturer Part Number
IDTTSE2002B3CNCG8
Description
IC TEMP SENS EEPROM TDFN-8
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDTTSE2002B3CNCG8.pdf
(30 pages)
Specifications of IDTTSE2002B3CNCG8
Function
Temp Monitoring System (Sensor)
Topology
ADC (Sigma Delta), Control Logic, Register Bank
Sensor Type
Internal
Sensing Temperature
-20°C ~ 125°C
Output Type
2-Wire Serial, I²C™/SMBUS™
Output Alarm
No
Output Fan
No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-20°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-WFDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-2034-2
Device Diagram
Device Interface
operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and R/W# bit
(as described in the I
optional I
and SA2 to generate an I
operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011).
data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Bus
Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ.
as 2 bytes, Most Significant Byte (MSB) first, and terminated with a NoAck and STOP after the Least Significant byte (LSB). Data and address infor-
mation is transmitted and received starting with the Most Significant Bit.first
The TSE2002B3C behaves as a slave device in the I
In accordance with the I
When writing data to the memory, the SPD inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When
The TS section of the device uses a pointer register to access all registers in the device.
Additionally, all data transfers to and from this section of the device are performed as block read/ write operations. The data is transmitted/received
2
C bus feature.
2
C Operating Mode table), terminated by an acknowledge bit. The TSE2002B3C does not initiate clock stretching which is an
2
C Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the PSWP,CSWP, or PSWP
2
C bus definition, the device uses three (3) built-in, 4-bit Device Type Identifier Codes (DTIC) and the state of SA0, SA1,
2
C protocol, with all memory operations synchronized by the serial clock. Read and Write
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May 12, 2010