IDTTSE2002B3CNCG8 IDT, Integrated Device Technology Inc, IDTTSE2002B3CNCG8 Datasheet - Page 17

• Manufacturer Part Number: IDTTSE2002B3CNCG8
• Description: IC TEMP SENS EEPROM TDFN-8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDTTSE2002B3CNCG8

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Control Logic, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -20°C ~ 125°C
• Output Type: 2-Wire Serial, I²C™/SMBUS™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-2034-2

Write Mode Sequences in a Non-Write Protected Area
Byte Write
replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with
Ack. The bus master terminates the transfer by generating a Stop condition, as shown in the Write Mode Sequence in a Non-Write Protected Area
figure above.
Page Write
that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as
“roll-over” occurs. This should be avoided, as data starts to be over-written in an implementation dependent fashion.
device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter is incre-
mented. The transfer is terminated by the bus master generating a Stop condition.
Write Cycle Polling Using ACK
cells. The maximum Write time (t
polling sequence can be used by the bus master.
•
•
•
After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is write-protected, the device
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory:
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device. If the addressed location is write-protected, the
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory
The polling sequence is shown in the following figure:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the
first byte of this instruction having been sent during Step 1).
W)
is shown in the AC Characteristic for TSE2002B3C table, but the typical time is shorter. To make use of this, a
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May 12, 2010