IDTTSE2002B3CNCG8 IDT, Integrated Device Technology Inc, IDTTSE2002B3CNCG8 Datasheet - Page 13

• Manufacturer Part Number: IDTTSE2002B3CNCG8
• Description: IC TEMP SENS EEPROM TDFN-8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDTTSE2002B3CNCG8

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Control Logic, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -20°C ~ 125°C
• Output Type: 2-Wire Serial, I²C™/SMBUS™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-2034-2

No Acknowledge Bit (NACK)
master releases Serial Data (SDA) after sending eight bits of data, and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low.
Data Input
must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven
Low.
Memory Addressing
sends the Device Select Code, shown in the next table (on Serial Data (SDA), most significant bit first).
Device Select Code
4-bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b; and to access the Temperature Sensor settings is 0011b.
inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable
(SA0, SA1, SA2) inputs.
the device does not match the SPD Device Select code, the SPD section deselects itself from the bus, and goes into Standby mode. The I
ating modes are shown in the following table.
Read/Write SPD Memory
Set Write Protection (SWP)
Clear Write Protection (CWP)
Permanently Set Write Protection (PSWP)
Read SWP
Read PSWP
Read/Write Temperature Registers
The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA)
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Select Address (SA2, SA1, SA0). To address the memory array, the
Up to eight memory devices can be connected on a single I
The 8th bit is the Read/Write bit (R/W#). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If
Notes:
1. The most significant bit, b7, is sent first.
2. SA0, SA1, and SA2 are compared against the respective external pins on the TSE2002B3C.
2
Memory Area
Function
2
b7
Device Type Identifier
1
0
0
1
2
C bus. Each one is given a unique 3-bit code on the Chip Enable (SA0, SA1, SA2)
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b6
0
1
0
b5
1
1
1
b4
0
0
1
V
V
V
SA2
SA2
SA2
SA2
SSSPD
SSSPD
SSSPD
b3
Select Address Signals
V
V
V
DDSPD
SA1
SA1
SA1
SA1
SSSPD
SSSPD
b2
V
V
V
SA0
SA0
SA0
SA0
b1
HV
HV
HV
May 12, 2010
R/W#
R/W#
R/W#
b0
0
0
0
1
1
2
C oper-