DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 12
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DP83816AVNG
Manufacturer Part Number
DP83816AVNG
Description
Ethernet Media Access Controller IC
Manufacturer
National Semiconductor
Datasheet
1.DP83816AVNG.pdf
(106 pages)
Specifications of DP83816AVNG
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Mounting Type
Surface Mount
Features
Physical Layer
Package / Case
144-LQFP
Package
144LQFP
Standard Supported
IEEE 802.3|IEEE 802.3u|IEEE 802.3x
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII
Data Rate
10|100 Mbps
Host Interface
PCI
Operating Supply Voltage
3.3 V
Loopback Mode
Internal
Maximum Power Dissipation
0.504 W
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83816AVNG
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83816AVNG
Manufacturer:
NS/国半
Quantity:
20 000
Company:
Part Number:
DP83816AVNG-EX/NOPB
Manufacturer:
National Semiconductor
Quantity:
135
Company:
Part Number:
DP83816AVNG-EX/NOPB
Manufacturer:
ADI
Quantity:
68
Company:
Part Number:
DP83816AVNG-EX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Company:
Part Number:
DP83816AVNG/NOPB
Manufacturer:
NS
Quantity:
5 000
Part Number:
DP83816AVNG/NOPB
Manufacturer:
NS/国半
Quantity:
20 000
3.0 Functional Description
3.1 MAC/BIU
The MAC/BIU is a derivative design from the DP83810
(Euphrates). The original MAC/BIU design has been
optimized to improve logic efficiency and enhanced to add
features consistent with current market needs and
specification compliance. The MAC/BIU design blocks are
discussed in this section.
3.1.1 PCI Bus Interface
This block implements PCI v2.2 bus protocols, and
configuration space. Supports bus master reads and writes
to CPU memory, and CPU access to on-chip register
space. Additional functions provided include: configuration
32
PCI Bus
Interface
EEPROM
93C46
Serial
32
32
32
32
32
Figure 3-2
32
15
(Continued)
Boot ROM/
MAC/BIU
Flash
Pkt Recog
Rx Filter
Rx Buffer Manager
Tx Buffer Manager
SRAM
MIB
Logic
Data FIFO
Data FIFO
Functional Block Diagram
12
control, serial EEPROM access with auto configuration
load, interrupt control, power management control with
support for PME or CLKRUN function.
3.1.1.1 Byte Ordering
The DP83816 can be configured to order the bytes of data
on the AD[31:0] bus to conform to little endian or big
endian ordering through the use of the Configuration
Register, bit 0 (CFG:BEM). By default, the device is in little
endian ordering. Byte ordering only affects data FIFOs.
Register information remains bit aligned (i.e. AD[31] maps
to bit 31 in any register space, AD[0] maps to bit 0, etc.).
16
32
32
MAC/BIU
Rx MAC
Tx MAC
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