DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 42

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.3 EEPROM Access Register
The EEPROM Access Register provides an interface for software access to the NMC9306 style EEPROM The default
values given assume that the EEDO line has a pullup resistor to VDD.
4.2.4 EEPROM Map
31-7
Bit
6
5
4
3
2
1
0
Bit Name
MDDIR
EESEL
EECLK
EEDO
MDIO
EEDI
MDC
Offset: 0008h
(Continued)
In the above table:
N denotes the value is dependent on the ethernet MAC ID Number.
X denotes the value is dependent on the checksum value.
Tag: MEAR
unused
MII Management Clock
Controls the value of the MDC pin. When set, the MDC pin is 1; when clear the MDC pin is 0. R/W
MII Management Direction
Controls the direction of the MDIO pin. When set, DP83816 drives the MDIO pin. When clear MDIO bit
reflects the current state of the MDIO pin. R/W
MII Management Data
Software access to the MDIO pin (see MDDIR above). R/W
EEPROM Chip Select
Controls the value of the EESEL pin. When set, the EESEL pin is 1; when clear the EESEL pin is 0. R/W
EEPROM Serial Clock
Controls the value of the EECLK pin. When set, the EECLK pin is 1; when clear the EECLK pin is 0. R/W
EEPROM Data Out
Returns the current state of the EEDO pin. When set, the EEDO pin is 1; when clear the EEDO pin is 0.
RO
EEPROM Data In
Controls the value of the EEDI pin. R/W
EEPROM
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
CFGSID[0:15]
CFGSID[16:31]
CFGINT[24:31],CFGINT[16:23]
CFGCS[20],PMCAP[31],PMCAP[21],PMCSR[8],
CFG[13:16],CFG[18:23],CR[2], SOPAS[0]
SOPAS[1:16]
SOPAS[17:32]
SOPAS[33:47],PMATCH[0]
PMATCH[1:16]
PMATCH[17:32]
PMATCH[33:47],WCSR[0]
WCSR[1:4],WCSR[9:10],RFCR[20],RFCR[22],
RFCR[27:31],000b (3 bits)
checksum value
Configuration/Operation Register Bits
Access: Read Write
Size: 32 bits
42
Description
Hard Reset: 00000002h
Soft Reset: 00000002h
Default Value
(16 bits)
NNNNh
NNNNh
NNNNh
2CD0h
D008h
CF82h
000Nh
0400h
0000h
0000h
A098h
XX55
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