DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 54

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.15 Wake Command/Status Register
The WCSR register is used to configure/control and monitor the DP83816 Wake On LAN logic. The Wake On LAN logic
is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the system if the
desired packet type, contents, or Link change are detected.
19-11
Bit
31
30
29
28
27
26
25
24
23
22
21
20
10
9
8
7
6
Bit Name
Reserved
MCASTR
SOHACK
BCASTR
UCASTR
WKMAG
WKPAT3
WKPAT2
WKPAT1
PHYINT
MPSOE
PATM3
PATM2
PATM1
PATM0
ARPR
MPR
Offset: 0040h
(Continued)
Tag: WCSR
Magic Packet Received
Set to 1 if a Magic Packet has been detected and the WKMAG bit is set. RO, cleared on read.
Pattern 3 match
Associated bit set to 1 if a pattern 3 match is detected and the WKPAT3 bit is set. RO, cleared on read.
Pattern 2 match
Associated bit set to 1 if a pattern 2 match is detected and the WKPAT2 bit is set. RO, cleared on read.
Pattern 1 match
Associated bit set to 1 if a pattern 1 match is detected and the WKPAT1 bit is set. RO, cleared on read.
Pattern 0 match
Associated bit set to 1 if a pattern 0 match is detected and the WKPAT0 bit is set. RO, cleared on read.
ARP Received
Set to 1 if an ARP packet has been detected and the WKARP bit is set. RO, cleared on read.
Broadcast Received
Set to 1 if a broadcast packet has been detected and the WKBCP bit is set. RO, cleared on read.
Multicast Received
Set to 1 if a multicast packet has been detected and the WKMCP bit is set. RO, cleared on read.
Unicast Received
Set to 1 if a unicast packet has been detected the WKUCP bit is set. RO, cleared on read.
Phy Interrupt
Set to 1 if a Phy interrupt was detected and the WKPHY bit is set. RO, cleared on read.
Reserved
RO, cleared on read.
SecureOn Hack Attempt
Set to 1 if the MPSOE and WKMAG bits are set, and a Magic Packet is receive with an invalid
SecureOn password value. RO, Cleared on read.
unused
returns 0
Magic Packet SecureOn Enable
Enable Magic Packet SecureOn feature. Only applicable when bit 9 is set. R/W
Wake on Magic Packet
Enable wake on Magic Packet detection. R/W
Wake on Pattern 3 match
Enable wake on match of pattern 3. R/W
Wake on Pattern 2 match
Enable wake on match of pattern 2. R/W
Wake on Pattern 1 match
Enable wake on match of pattern 1. R/W
Access: Read Write
Size: 32 bits
54
Description
Hard Reset: 00000000h
Soft Reset: 00000000h
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