DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 86

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.0 Buffer Management
5.3.2 Receive Data Flow
With a bus mastering architecture, some number of buffers
and descriptors for received packets must be pre-allocated
when the DP83816 is initialized. The number allocated will
directly affect the system's tolerance to interrupt latency.
The more buffers that you pre-allocate, the longer the
system will survive an incoming burst without losing
receive packets, if receive descriptor processing is delayed
or preempted. Buffers sizes should be allocated in 32 byte
multiples.
1. Prior to packet reception, receive buffers must be
2. The address of the first descriptor in this list is then
described in a receive descriptor list (or ring, if
preferred). In each descriptor, the driver assigns
ownership to the hardware by clearing the OWN bit.
Receive descriptors may describe a single buffer.
written to the RXDP register. As packets arrive, they
are placed in available buffers. A single packet may
occupy one or more receive descriptors, as required
by the application.The device reads in the first
descriptor into the RxDescCache.
rxDescRefr
XferDone
XferDone
rxAdvance
link = NULL
rxDescWrite
CR:RXE && CRDD
(Continued)
(descCnt == 0) && (rxPktBytes > 0)
Figure 5-7 Receive State Diagram
link != NULL
rxPktBytes == 0
rxIdle
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If the receive buffer management state machine runs out of
descriptors while receiving a packet, data will buffer in the
receive FIFO. If the FIFO overflows, the driver will be
interrupted with an RxOVR error.
rxFifoBlock
3. As data arrives in the RxDataFIFO, the receive buffer
4. If end of packet was reached, the status in the
management state machine places the data in the
receive buffer described by the descriptor. This
continues until either the end of packet is reached, or
the descriptor byte count for this descriptor is
reached.
descriptor (in main memory) is updated by setting the
OWN bit and clearing the MORE bit, by updating the
receive status bits as indicated by the MAC, and by
updating the SIZE field. The status bits in cmdsts are
only valid in the last descriptor of a packet (with the
MORE bit clear). Also for the last descriptor of a
packet, the SIZE field will be updated to reflect the
actual amount of data written to the buffer (which
may be less the full buffer size allocated by the
descriptor).
XferDone && OWN
rxDescRead
CR:RXE && !CRDD
XferDone && !OWN
FifoReady
XferDone
rxFragWrite
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