DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 8

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.0 Pin Description
100BASE-TX/10BASE-T Interface
BIOS ROM/Flash Interface
Note: DP83816 supports NM27LV010 for the BIOS ROM interface device.
TPTDP, TPTDM
TPRDP, TPRDM
MCSN
MD7, MD6, MD5,
MD4/EEDO, MD3,
MD2,
MD1/CFGDISN,
MD0
MA5,
MA4/EECLK,
MA3/EEDI,
MA2/LED100LNK,
MA1/LED10LNK,
MA0/LEDACT
MWRN
MRDN
Symbol
Symbol
141, 140, 139,
LQFP Pin
LQFP Pin
138, 135,
54, 53
46, 45
No(s)
No(s)
134,
133,
144,
143,
129
132
142
131
130
3,
2,
1,
(Continued)
A-O
Dir
Dir
A-I
I/O
O
O
O
O
Transmit Data: Differential common output driver. This differential common output
is configurable to either 10BASE-T or 100BASE-TX signaling:
10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as
Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes).
100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.
The DP83816 will automatically configure this common output driver for the proper
signal type as a result of either forced configuration or Auto-Negotiation.
Receive Data: Differential common input buffer. This differential common input can
be configured to accept either 100BASE-TX or 10BASE-T signaling:
10BASE-T: Reception of Manchester encoded 10BASE-T packet data as well as
normal Link Pulses and Fast Link Pulses for Auto-Negotiation purposes.
100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data.
The DP83816 will automatically configure this common input buffer to accept the
proper signal type as a result of either forced configuration or Auto-Negotiation.
BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash access, this signal is
used to select the ROM device.
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these signals are
used to transfer data to or from the ROM/Flash device.
MD[5:0] pins have internal weak pull ups.
MD6 and MD7 pins have internal weak pull downs.
BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these signals are
used to drive the ROM/Flash address.
BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is used to
enable data to be written to the Flash device.
BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is used to
enable data to be read from the Flash device.
8
Description
Description
www.national.com