DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 84

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.0 Buffer Management
5.3 Receive Architecture
The receive architecture is as "symmetrical" to the transmit
architecture as possible. The receive buffer manager
prefetches receive descriptors to prepare for incoming
When the RXE bit is set to 1 in the CR register (regardless
of the current state), and the DP83816 receive state
machine is idle, then DP83816 will read the contents of the
descriptor referenced by RXDP into the Rx Descriptor
Cache. The Rx Descriptor Cache allows the DP83816 to
5.3.1 Receive State Machine
The receive state machine has the following states:
The receive state machine manipulates the following internal data spaces:
Inputs to the receive state machine include the following events:
rxIdle
rxDescRefr
rxDescRead
rxFifoBlock
rxFragWrite
rxDescWrite
RXDP
CRDD
RxDescCache An internal data space equal to the size of the maximum receive descriptor supported.
descCnt
fragPtr
rxPktCnt
rxPktBytes
CR:RXE
XferDone
FifoReady
link
cmdsts
ptr
Receive Descriptor List
The receive state machine is idle.
Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.
Waiting for the transfer of a descriptor from the PCI bus into the RxDescCache.
Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to represent a
complete packet.
Waiting for the transfer of data from the RxDataFIFO via the PCI bus to host memory.
Waiting for the completion of the write of the cmdsts field of a receive descriptor.
A 32-bit register that points to the current receive descriptor.
An internal bit flag that is set when the current receive descriptor has been completed, and ownership
has been returned to the driver. It is cleared whenever RXDP is loaded with a new value (either by the
state machine, or the driver).
Count of bytes available for storing receive data in all fragments described by the current descriptor.
Pointer to the next unwritten byte in the current fragment.
Number of packets in the rxDataFifo. Incremented by the MAC (the fill side of the FIFO). Decremented
by the receive state machine as packets are processed.
Number of bytes in the current packet being drained from the rxDataFifo, that are in fact currently in the
rxDataFifo (Note: packets larger than FIFO size, this number will never be greater than the FIFO size).
The RXE bit in the Command Register has been set.
completion of a PCI bus transfer request.
(rxPktCnt > 0) or (rxPktBytes > rxDrainThreshold)... in other words, if we have a complete packet in the
FIFO (regardless of size), or the number of bytes that we do have is greater than the rxDrainThreshold,
then we are ready to begin draining the rxDataFifo.
link
cmdsts
ptr
(Continued)
Figure 5-6 Receive Architecture
Software/Memory
link
cmdsts
ptr
84
packets. When the amount of receive data in the
RxDataFIFO is more than the RxDrainThreshold, or the
RxDataFIFO contains a complete packet, then the state
machine begins filling received buffers in host memory.
read an entire descriptor in a single burst, and reduces the
number of bus accesses required for fragment information
to 1. The DP83816 Rx Descriptor Cache holds a single
buffer pointer/count combination.
Hardware
RxHead
link
cmdsts
ptr
Rx DMA
Rx Descriptor Cache
Rx Data FIFO
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