DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 47

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.0 Register Set
4.2.8 Interrupt Enable Register
The Interrupt Enable Register controls the hardware INTR signal.
4.2.9 Interrupt Holdoff Register
The Interrupt Holdoff Register provides interrupt holdoff support. This allows interrupts to be delayed based on a
programmable delay timer.
When Interrupts are enabled IE = 1, and IH contains a value other than 00h, IHCTL determines when the Interrupt
Holdoff timer will begin its countdown as such:
When IH = 00h (default), there is no delay applied regardless of what IHCTL is set to.
31-1
31-9
Bit
Bit
7-0
0
8
Bit Name
Bit Name
IHCTL = 1:
IHCTL = 0:
IHCTL
IE
IH
Offset: 0018h
Offset: 001Ch
(Continued)
Tag: IER
Tag: IHR
unused
Interrupt Enable
When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR signal will be
masked, and no interrupts will be generated. The setting of this bit has no effect on the ISR or IMR. This
provides the ability to disable the hardware interrupt to the host with a single access (eliminating the
need for a read-modify-write cycle). The actual enabling of interrupts can be delayed based on the
Interrupt Holdoff Register defined in the following section. If IE = 0, the interrupt holdoff timer will not
start.
unused
Interrupt Holdoff Control
If this bit is set, the interrupt holdoff timer will start when the first interrupt event occurs and interrupts are
enabled. When this bit is not set, the interrupt holdoff timer will start as soon as the timer is loaded and
interrupts are enabled. In other words, when not set, the timer will delay the interrupt enable.
Interrupt Holdoff
The register contains a counter value for use in preventing interrupt assertion for a programmed amount
of time. When the ISR is read, the interrupt holdoff timer is loaded with this value. It begins to count down
to 0 based on the setting of the IHCTL bit. Once it reaches 0, interrupts will be enabled. The counter
value is in units of 100 µs.
The timer does not begin until an interrupt event occurs.
The reporting of an interrupt event is delayed for a fixed amount of time from when the
interrupt occurs.
The timer begins immediately without waiting for an interrupt event.
The reporting of an interrupt event is delayed for a non-fixed amount of time from when the
interrupt occurs.
Access: Read Write
Access: Read Write
Size: 32 bits
Size: 32 bits
47
Description
Description
Hard Reset: 00000000h
Hard Reset: 00000000h
Soft Reset: 00000000h
Soft Reset: 00000000h
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