C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 137
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C8051F124TB
Manufacturer Part Number
C8051F124TB
Description
MCU, MPU & DSP Development Tools With C8051F124 MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F124TB
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). This
function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) is provided in Table 11.2. in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Note that certain SFR’s are accessible from ALL SFR pages, and are denoted by the “ (ALL
PAGES) ” designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “ (ALL PAGES) ”
designation, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE regis-
ter value.
CIP-51
Interrupt
Logic
Figure 11.4. SFR Page Stack
SFRPGCN Bit
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
SFRPAGE
SFRNEXT
SFRLAST
C8051F130/1/2/3
137
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