C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 171

• Manufacturer Part Number: C8051F124TB
• Description: MCU, MPU & DSP Development Tools With C8051F124 MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F124TB

• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bits 7 – 4: UNUSED: Read = 0000b, Write = don’t care.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
*Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
Bits 7 – 0: High Byte (bits 15 – 8) of MAC0 A Register.
Bit7
Bit7
R
R
-
MAC0HO: Hard Overflow Flag.
This bit is set to ‘1’ whenever an overflow out of the MAC0OVR register occurs during a
MAC operation (i.e. when MAC0OVR changes from 0x7F to 0x80 or from 0x80 to 0x7F).
The hard overflow flag must be cleared in software by directly writing it to ‘0’, or by resetting
the MAC logic using the MAC0CA bit in register MAC0CF.
MAC0Z: Zero Flag.
This bit is set to ‘1’ if a MAC0 operation results in an Accumulator value of zero. If the result
is non-zero, this bit will be cleared to ‘0’.
MAC0SO: Soft Overflow Flag.
This bit is set to ‘1’ when a MAC operation causes an overflow into the sign bit (bit 31) of the
MAC0 Accumulator. If the overflow condition is corrected after a subsequent MAC opera-
tion, this bit is cleared to ‘0’.
MAC0N: Negative Flag.
If the MAC Accumulator result is negative, this bit will be set to ‘1’. If the result is positive or
zero, this flag will be cleared to ‘0’.
Bit6
Bit6
R
R
-
SFR Definition 12.3. MAC0AH: MAC0 A High Byte
SFR Definition 12.2. MAC0STA: MAC0 Status
Bit5
Bit5
R
R
-
Bit4
Bit4
R
R
-
MAC0HO
Rev. 1.4
R/W
Bit3
Bit3
R
C8051F120/1/2/3/4/5/6/7
MAC0Z
R/W
Bit2
Bit2
R
MAC0SO
C8051F130/1/2/3
R/W
Bit1
Bit1
R
SFR Address: 0xC0
SFR Address: 0xC2
MAC0N 00000100
SFR Page: 3
SFR Page: 3
R/W
Bit0
Bit0
R
Addressable
00000000
Reset Value
Reset Value
Bit
171