C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 28
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C8051F124TB
Manufacturer Part Number
C8051F124TB
Description
MCU, MPU & DSP Development Tools With C8051F124 MCU
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F124TB
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.1.3. Additional Features
Several key enhancements are implemented in the CIP-51 core and peripherals to improve overall perfor-
mance and ease of use in end applications.
The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the stan-
dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput. The extra inter-
rupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board V
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input
pin, and the RST pin. The RST pin is bi-directional, accommodating an external reset, or allowing the inter-
nally generated POR to be output on the RST pin. Each reset source except for the V
Input pin may be disabled by the user in software; the V
pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU ini-
tialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter-
nal crystal source, while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally,
an on-chip PLL is provided to achieve higher system clock speeds for increased throughput.
28
(Port I/O)
XTAL1
XTAL2
CP0+
CP0-
Generator
Circuitry
Internal
Clock
OSC
Crossbar
PLL
Comparator0
CNVSTR
+
-
(CNVSTR
enable)
reset
Figure 1.7. On-Board Clock and Reset
enable)
(CP0
reset
Clock Select
System
Clock
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Core
Handler
V
Rev. 1.4
DD
EN
WDT
PRE
DD
Supply
Monitor
+
-
Software Reset
System Reset
monitor is enabled/disabled via the MONEN
DD
Timeout
Supply
Reset
monitor, a Watchdog Timer, a missing
(wired-OR)
Reset
Funnel
DD
monitor and Reset
RST
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