FPAL20SL60 Fairchild Semiconductor, FPAL20SL60 Datasheet - Page 11

• Manufacturer Part Number: FPAL20SL60
• Description: IGBT Transistors 600V/20A/SPM
• Manufacturer: Fairchild Semiconductor

Specifications of FPAL20SL60

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2002 Fairchild Semiconductor Corporation
Recommended Operating Conditions
ICs Internal Structure and Input/Output Conditions
Note
1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to R
2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs
3. Each IC has under voltage detection and protection function.
4. The logic input is compatible with standard CMOS or LSTTL outputs.
5. R
6. It would be recommended that the bootstrap diode, D
Supply Voltage
Control Supply Voltage
High-side Bias Voltage
Blanking Time for Preventing
Arm-short
PWM Input Signal
Input ON Threshold Voltage
Input OFF Threshold Voltage
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs
SPM gating input pin.
P
C
15V Line
15V Line
15V Line
15V Line
P
coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
C
C
R
R
5V Line
5V Line
5V Line
5V Line
5V Line
5V Line
5V Line
5V Line
PH
P
P
PL
C
C
Item
FOD
BP15
R
C
PF
PF
IN IN IN IN
VCC
VCC
V V V V
COM
COM
VCC
VCC
C C C C
VCC
VCC
IN IN IN IN
COM
COM
VCC
VCC
FO
FO
FO
FO
FOD
FOD
(UL,VL,WL)
(UL,VL,WL)
(UL,VL,WL)
(UL,VL,WL)
FOD
FOD
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
(L)
(L)
(L)
(L)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
FAULT OUTPUT
(HYSTERISIS)
REFERENCE
GENERATOR
DETECT
BANDGAP
DURATION
Symbol
V
PULSE
V
UV
IN(OFF)
f
t
V
IN(ON)
V
V
PWM
dead
CC
PN
BS
GENERATOR
PULSE
BS
R
DELAY
BS
Applied between P - N
Applied between V
Applied between V
V
For Each Input Signal
T
Applied between U
Applied between U
TIME
, has soft and fast recovery characteristics.
LEVEL
SHIFT
C
B(W)
100°C, T
- V
PROTECTION
PROTECTION
LATCH_UP
LATCH_UP
S(W)
UV
SC
UV
SC
Fig. 11.
J
D
DETECT
PULSE
FILTER
BS
UV
125°C
DELAY
Condition
TIME
CC(H)
B(U)
IN
IN
,V
,V
HVIC
HVIC
HVIC
HVIC
LVIC
LVIC
LVIC
LVIC
IN
IN
- V
R
R
S Q
- COM, V
, W
, W
DETECTION
S(U)
SOFT_OFF
BUFFER
CONTROL
IN
IN
SC
, V
- COM
- COM
B(V)
CC(L)
VS
VS
VS
VS
VB
VB
VB
VB
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
- V
(UL,VL,WL)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
(UH,VH,WH)
OUTPUT
- COM
S(V)
C
,
BS
C
SC
Min.
13.5
13.5
C
3
BSC
-
-
R
0 ~ 0.65
F
4 ~ 5.5
Value
Typ.
300
15
15
3
-
R
SC
SC
Max.
16.5
16.5
400
terminal to detect
Rev. B1, February 2002
-
-
U,V,W
U,V,W
U,V,W
U,V,W
N N N N
P P P P
Unit
kHz
us
V
V
V
V
V