AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9268BCPZ-105
Manufacturer:
Analog Devices Inc.
Quantity:
236
FEATURES
SNR = 78.2 dBFS @ 70 MHz and 125 MSPS
SFDR = 88 dBc @ 70 MHz and 125 MSPS
Low power: 750 mW @ 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.6 dBm/Hz small-signal input noise with 200 Ω input
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
impedance @ 70 MHz and 125 MSPS
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Analog-to-Digital Converter (ADC)
SENSE
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
RBIAS
VIN+A
VIN–B
VIN+B
VIN–A
VREF
VCM
SEE FIGURE 7 FOR LVDS PIN NAMES.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
Pin compatibility with the AD9258, allowing a simple
migration from 16 bits to 14 bits. The AD9268 is also pin
compatible with the AD9251, AD9231, and
of products for lower sample rate, low power applications.
AGND
SELECT
AD9268
REF
FUNCTIONAL BLOCK DIAGRAM
AVDD
MULTICHIP
SYNC
SYNC
ADC
ADC
©2009 Analog Devices, Inc. All rights reserved.
PROGRAMMING DATA
SDIO/
DUTY CYCLE
DCS
STABILIZER
DIVIDE 1
Figure 1.
PDWN
TO 8
SCLK/
DFS
SPI
OUTPUT BUFFER
OUTPUT BUFFER
CMOS/LVDS
CMOS/LVDS
CSB
GENERATION
OEB
DCO
DRVDD
16
16
AD9268
www.analog.com
AD9204
ORA
D15A (MSB)
TO
D0A (LSB)
CLK+
CLK–
DCOA
DCOB
ORB
D15B (MSB)
TO
D0B (LSB)
family

AD9268BCPZ-105 Summary of contents

Page 1

FEATURES SNR = 78.2 dBFS @ 70 MHz and 125 MSPS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply ...

Page 2

AD9268 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ................................................................. 6 ...

Page 3

GENERAL DESCRIPTION The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The dual ADC core ...

Page 4

... POWER SUPPLIES Supply Voltage AVDD Full DRVDD Full Supply Current IAVDD 1 Full 1 IDRVDD (1.8 V Full CMOS) 1 IDRVDD (1.8 V Full LVDS) AD9268BCPZ-80 AD9268BCPZ-105 Min Typ Max Min Typ 16 16 Guaranteed Guaranteed ±0.2 ±0.4 ±0.2 ±0.4 ±2.5 ±0.4 −1.0 +1.4 −1.0 ±0.65 ±0.7 ± ...

Page 5

... Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). AD9268BCPZ-80 AD9268BCPZ-105 Min Typ Max Min Typ ...

Page 6

... MHz 140 MHz 200 MHz IN With On-Chip Dither (AIN @ −23 dBFS 2.4 MHz MHz 140 MHz 200 MHz IN AD9268BCPZ-80 AD9268BCPZ-105 Temp Min Typ Max Min 25°C 79.7 25°C 78.3 79.0 77.2 Full 78.0 77.1 25°C 77.4 25°C 75.5 25°C 79.4 25°C 78 ...

Page 7

... SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance AD9268BCPZ-80 AD9268BCPZ-105 Temp Min Typ Max Min 25°C −99 25°C −100 −96 Full − ...

Page 8

AD9268 Parameter 1 LOGIC INPUT (CSB) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance 2 LOGIC INPUT (SCLK/DFS) High Level Input Voltage Low Level Input Voltage High Level ...

Page 9

... Full −0.6 −0.4 0 Full 2.9 3.7 4.5 Full 3.9 Full −0.1 +0.2 +0.5 Full 12 Full 12/12.5 Full 500 Full 2 Rev Page AD9268BCPZ-105 AD9268BCPZ-125 Min Typ Max Min Typ 625 20 105 20 10 105 10 9.5 8 2.85 4.75 6.65 2.4 4 4.5 4.75 5.0 3 ...

Page 10

AD9268 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time SSYNC t SYNC to rising edge of CLK+ hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and ...

Page 11

N – 1 VIN t CH CLK+ CLK– t DCO DCOA/DCOB A/CH B DATA Figure 4. LVDS Mode Data Output Timing CLK+ t SSYNC SYNC Figure 5. SYNC Input Timing Requirements ...

Page 12

AD9268 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter 1 ELECTRICAL AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to ...

Page 13

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D0B (LSB) DRVDD NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Table 8. ...

Page 14

AD9268 Pin No. Mnemonic 33 D7A 34 D8A 35 D9A 36 D10A 38 D11A 39 D12A 40 D13A 41 D14A 42 D15A (MSB) 43 ORA 4 D0B (LSB) 5 D1B 6 D2B 7 D3B 8 D4B 9 D5B 11 D6B ...

Page 15

D0– (LSB) D0+ (LSB) DRVDD NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Table 9. Pin Function Descriptions ...

Page 16

AD9268 Pin No. Mnemonic 11 D3− 14 D4+ 13 D4− 16 D5+ 15 D5− 18 D6+ 17 D6− 21 D7+ 20 D7− 23 D8+ 22 D8− 27 D9+ 26 D9− 30 D10+ 29 D10− 32 D11+ 31 D11− 34 D12+ ...

Page 17

TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference p-p differential input, VIN = −1.0 dBFS, and 32k sample 25°C, unless otherwise noted ...

Page 18

AD9268 120 110 100 SNRFS (DITHER ON) SNRFS (DITHER OFF) 90 SFDRFS (DITHER ON) SFDRFS (DITHER OFF –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 14. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude ( ...

Page 19

SNR = 78.2dB (79.2dBFS) SFDR = 90dBc –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 20. AD9268-105 Single-Tone FFT with f 0 105MSPS 70.1MHz @ ...

Page 20

AD9268 120 110 100 SNRFS (DITHER ON) SNRFS (DITHER OFF) 90 SFDRFS (DITHER ON) SFDRFS (DITHER OFF –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 26. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (A with f ...

Page 21

SNR = 77.7dB (78.7dBFS) SFDR = 90dBc –40 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 –140 FREQUENCY (MHz) Figure 32. AD9268-125 Single-Tone FFT with f 0 125MSPS 30.3MHz ...

Page 22

AD9268 0 125MSPS 70.1MHz @ –6dBFS –20 SNR = 72.2dB (78.2dBFS) SFDR = 97dBc –40 –60 –80 SECOND HARMONIC THIRD HARMONIC –100 –120 –140 FREQUENCY (MHz) Figure 38. AD9268-125 Single-Tone FFT with f with Dither Enabled ...

Page 23

INPUT FREQUENCY (MHz) Figure 44. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (f with 2 V p-p Full Scale 95 90 SFDR (dBc SNR (dBFS) ...

Page 24

AD9268 100 SFDR (dBc), CHANNEL SFDR (dBc), CHANNEL A SNR (dBFS), CHANNEL B 80 SNR (dBFS), CHANNEL SAMPLE RATE (MSPS) Figure 50. AD9268-125 Single-Tone SNR/SFDR vs. Sample ...

Page 25

EQUIVALENT CIRCUITS VIN Figure 55. Equivalent Analog Input Circuit AVDD 0.9V 10kΩ 10kΩ CLK+ Figure 56. Equivalent Clock Input Circuit DRVDD PAD Figure 57. Digital Output DRVDD 350Ω SDIO/DCS Figure 58. Equivalent SDIO/DCS Circuit DRVDD 350Ω SCLK/DFS OR OEB Figure ...

Page 26

AD9268 THEORY OF OPERATION The AD9268 dual-core analog-to-digital converter (ADC) design can be used for diversity reception of signals, in which the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be ...

Page 27

Common-Mode Voltage Servo In applications where there may be a voltage loss between the VCM output of the AD9268 and the analog inputs, the common-mode voltage servo can be enabled. When the inputs are ac-coupled and a resistance of >100 ...

Page 28

AD9268 The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second ...

Page 29

VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9268. The input range can be adjusted by varying the reference voltage applied to the AD9268, using either the internal reference or an externally applied reference voltage. The ...

Page 30

AD9268 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 ...

Page 31

In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applica- tions, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed ...

Page 32

AD9268 POWER DISSIPATION AND STANDBY MODE As shown in Figure 81, the power dissipated by the AD9268 varies with its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers ...

Page 33

As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin ...

Page 34

AD9268 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9268 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the ...

Page 35

SERIAL PORT INTERFACE (SPI) The AD9268 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...

Page 36

AD9268 HARDWARE INTERFACE The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9268. The SCLK pin and the CSB pin function as inputs when using the SPI. The ...

Page 37

MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel ...

Page 38

AD9268 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Address Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration ...

Page 39

Address Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open (global) 0x0F ADC input Open Open (global) 0x10 Offset adjust (local) 0x14 Output mode Drive Output strength type 0 = ANSI 0 = CMOS LVDS; 1 ...

Page 40

AD9268 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only ...

Page 41

APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9268 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain ...

Page 42

... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9268BCPZ-80 −40°C to +85°C 1 AD9268BCPZRL7-80 −40°C to +85°C 1 AD9268BCPZ-105 −40°C to +85°C 1 AD9268BCPZRL7-105 −40°C to +85°C 1 AD9268BCPZ-125 −40°C to +85°C AD9268BCPZRL7-125 1 −40°C to +85°C 1 AD9268-80EBZ 1 AD9268-105EBZ ...

Page 43

NOTES Rev Page AD9268 ...

Page 44

AD9268 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08123-0-9/09(A) Rev Page ...

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