AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 30
Manufacturer Part Number
Dual 16 Bit 105 High SNR ADC
Analog Devices Inc
Specifications of AD9268BCPZ-105
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
Sampling Rate (per Second)
Number Of Converters
Power Dissipation (max)
Voltage Supply Source
Analog and Digital
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 62). The internal buffer generates the positive
and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9268 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
Clock Input Options
The AD9268 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9268 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
Figure 74. Equivalent Clock Input Circuit
Figure 73. Typical VREF Drift
VREF = 1.0V
Rev. A | Page 30 of 44
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9268 to approx-
imately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9268 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The AD9510/AD9511/AD9512/
drivers offer excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9518 clock drivers offer excellent jitter performance.
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 78. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 77. Differential PECL Sample Clock (Up to 625 MHz)