AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 29

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9268.
The input range can be adjusted by varying the reference voltage
applied to the AD9268, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
Internal Reference Connection
A comparator within the AD9268 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full-
scale input. In this mode, with SENSE grounded, the full scale can
also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of
Register 0x18. These bits can be used to change the full scale to
1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p,
as shown in Table 17.
Connecting the SENSE pin to the VREF pin switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output for a 1 V p-p full-scale input.
Table 11. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
1.0µF
Figure 70. Internal Reference Configuration
VIN+A/VIN+B
VIN–A/VIN–B
0.1µF
SENSE
VREF
SELECT
LOGIC
SENSE Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
AD9268
0.5V
CORE
ADC
Resulting VREF (V)
N/A
0.5
1.0
0.5
×
Rev. A | Page 29 of 44
1
+
R2
R1
(see Figure 71)
If a resistor divider is connected external to the chip, as shown
in Figure 71, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output, defined as follows:
The input range of the ADC always equals twice the voltage at
the reference pin (VREF) for either an internal or an external
reference.
If the internal reference of the AD9268 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 72 shows
how the internal reference voltage is affected by loading.
VREF
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
1.0µF
0
0.2
Figure 72. Reference Voltage Accuracy vs. Load Current
Figure 71. Programmable Reference Configuration
=
0
0.4
5 .
0.1µF
×
VREF
⎛ +
0.6
1
VIN+A/VIN+B
VIN–A/VIN–B
Resulting Differential Span (V p-p)
2 × external reference
1.0
2 × VREF
2.0
R2
R1
SENSE
R2
R1
0.8
LOAD CURRENT (mA)
1.0
1.2
VREF = 1V
SELECT
LOGIC
1.4
AD9268
VREF = 0.5V
0.5V
1.6
CORE
ADC
1.8
AD9268
2.0

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