AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 39

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9268BCPZ-105
Manufacturer:
ADI
Quantity:
530
Address
(Hex)
0x0E
0x0F
0x10
0x14
0x16
0x17
0x18
0x24
0x25
0x30
Digital Feature Control
0x100
Register
Name
BIST enable
(global)
ADC input
(global)
Offset adjust
(local)
Output mode
Clock phase
control
(global)
DCO output
delay (global)
VREF select
(global)
BIST signature
LSB (local)
BIST signature
MSB (local)
Dither enable
(local)
Sync control
(global)
Bit 7
(MSB)
Open
Open
Drive
strength
0 = ANSI
LVDS;
1 =
reduced
swing
LVDS
(global)
Invert
DCO clock
Open
Reference voltage
selection
(default)
Open
Open
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p
Bit 6
Open
Open
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Bit 5
Open
Open
CMOS
output
interleave
enable
(global)
Open
Open
Open
Open
Open
Offset adjust in LSBs from +127 to −128
(twos complement format)
Open
Open
Open
Bit 4
Output
enable
bar
(local)
Open
Open
Dither
enable
Rev. A | Page 39 of 44
BIST signature[15:8]
BIST signature[7:0]
Bit 3
Open
Open
Open
Open
Open
Open
(must be
written
Open
low)
(delay = 2500 ps × register value/31)
DCO clock delay
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
11110 = 2419 ps
11111 = 2500 ps
Bit 2
Reset BIST
sequence
Open
Output
invert
(local)
Open
Clock
divider
next sync
only
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Open
Bit 1
Open
Open
Open
Clock
divider
sync
enable
Output format
00 = offset binary
01 = twos
complement
01 = gray code
11 = offset binary
(local)
Bit 0
(LSB)
BIST
enable
Common-
mode
servo
enable
Open
Master
sync
enable
Open
0x00
0x00
0x00
0x00
Default
Value
(Hex)
0x04
0x00
0x00
0x00
0x00
0xC0
0x00
AD9268
Default
Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
Read only
Read only

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