ADUC7061BCPZ32 Analog Devices Inc, ADUC7061BCPZ32 Datasheet - Page 51

• Manufacturer Part Number: ADUC7061BCPZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Package: 32LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 10.24 MHz
• Operating Supply Voltage: 2.5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 14
• Interface Type: I2C/SPI/UART
• On-chip Adc: 2(4-chx24-bit)
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Primary Channel ADC Threshold Register
Name:
Address:
Default value:
Access:
Function:
Table 57. ADC0TH MMR Bit Designations
Bit
15:0
Primary Channel ADC Threshold Counter Limit Register
Name:
Address:
Default value:
Access:
Function:
Table 58. ADC0THC MMR Bit Designations
Bit
15:8
7:0
Description
Reserved.
ADC0 8-bit threshold counter limit register.
ADC0TH
0xFFFF053C
0x0000
Read and write
This 16-bit MMR sets the threshold against
which the absolute value of the primary ADC
conversion result is compared. In unipolar
mode, ADC0TH[15:0] are compared, and in
twos complement mode, ADC0TH[14:0] are
compared.
Description
ADC0 16-bit comparator threshold register.
ADC0THC
0xFFFF0540
0x0001
Read and write
This 8-bit MMR determines how many
cumulative (values below the threshold
decrement or reset the count to 0) primary
ADC conversion result readings above
ADC0TH must occur before the primary
ADC comparator threshold bit is set in the
ADCSTA MMR, generating an ADC
interrupt. The primary ADC comparator
threshold bit is asserted as soon as
ADC0THV = ADC0RCR.
Rev. B | Page 51 of 108
Primary Channel ADC Threshold Counter Register
Name:
Address:
Default value:
Access:
Function:
Table 59. ADC0THV MMR Bit Designations
Bit
7:0
Primary Channel ADC Accumulator Register
Name:
Address:
Default value:
Access:
Function:
Table 60. ADC0ACC MMR Bit Designations
Bit
31:0
Description
ADC0 8-bit threshold exceeded counter register.
Description
ADC0 32-bit accumulator register.
ADC0ACC
0xFFFF0548
0x00000000
Read only
This 32-bit MMR holds the primary ADC
accumulator value. The primary ADC ready bit
in the ADCSTA MMR should be used to
determine when it is safe to read this MMR.
The MMR value is reset to 0 by disabling the
accumulator in the ADCCFG MMR or by
reconfiguring the primary channel ADC.
ADC0THV
0xFFFF0544
0x0000
Read only
This 8-bit MMR is incremented every time
the absolute value of a primary ADC
conversion result |Result| ≥ ADC0TH. This
register is decremented or reset to 0 every
time the absolute value of a primary ADC
conversion result |Result| < ADC0TH. The
configuration of this function is enabled via
the primary channel ADC comparator bits in
the ADCCFG MMR.
ADuC7060/ADuC7061