ADUC7061BCPZ32 Analog Devices Inc, ADUC7061BCPZ32 Datasheet - Page 8

DUAL 24-BIT AFE AND ARM 7 I.C

ADUC7061BCPZ32

Manufacturer Part Number
ADUC7061BCPZ32
Description
DUAL 24-BIT AFE AND ARM 7 I.C
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7061BCPZ32

Design Resources
USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Core Processor
ARM7
Core Size
16/32-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 2.625 V
Data Converters
A/D 5x24b, 8x24b, D/A 1x14b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LFCSP
Package
32LFCSP EP
Device Core
ARM7TDMI
Family Name
ADuC7xxx
Maximum Speed
10.24 MHz
Operating Supply Voltage
2.5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
14
Interface Type
I2C/SPI/UART
On-chip Adc
2(4-chx24-bit)
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADuC7060/ADuC7061
Parameter
EXCITATION CURRENT SOURCES
WATCHDOG TIMER (WDT)
FLASH/EE MEMORY
DIGITAL INPUTS
LOGIC INPUTS
LOGIC OUTPUTS
CRYSTAL OSCILLATOR
ON-CHIP OSCILLATORS
MCU CLOCK RATE
MCU START-UP TIME
Output Current
Initial Tolerance at 25°C
Drift
Initial Current Matching at 25°C
Drift Matching
Line Regulation (AVDD)
Output Compliance
Using an External Clock to
At Power-On
After Reset Event
From MCU Power-Down
Timeout Period
Timeout Step Size
Endurance
Data Retention
Input Leakage Current
Input Pull-Up Current
Input Capacitance
Input Leakage Current
Input Pull-Down Current
Input Low Voltage (VINL)
Input High Voltage (VINH)
Output Low Voltage (VOL)
Output High Voltage (VOH)
Logic Inputs, XTALI Only
XTALI Capacitance
XTALO Capacitance
Oscillator
Input High Voltage (VINH)
P2.0/EXTCLK Pin
PLL On
PLL Off
Input Low Voltage (VINL)
Accuracy
1
Wake-Up from Interrupt
Wake-Up from Interrupt
Internal PLL Lock Time
16
1
1
1
17
1
1
1
1
1
Test Conditions/Comments
Available from each current
source
Matching between both current
sources
AVDD = 2.5 V ± 5%
32.768 kHz clock, 256 prescale
All digital inputs except NTRST
Input (high) = DVDD
Input (low) = 0 V
NTRST only: input (low) = 0 V
NTRST only: input (high) = DVDD
All logic inputs
All logic outputs except XTALO
I
I
Eight programmable core clock
selections within this range:
binary divisions 1, 2, 4, 8 . . . 64, 128
Includes kernel power-on
execution time
Includes kernel power-on
execution time
CD = 0
CD = 0
SOURCE
SOURCE
= 1.6 mA
= 1.6 mA
Rev. B | Page 8 of 108
Min
200
AVDD − 0.7 V
0.008
10,000
20
10
30
2.0
2.0
1.7
−3
0.08
0.08
Typ
1000
±5
0.06
±0.5
20
0.2
7.8
±1
20
10
±1
55
12
12
32,768
1.28
134
5
4.8
66
1
Max
AGND − 30 mV
512
±10
80
±10
100
0.4
0.6
0.8
+3
10.24
10.24
Unit
μA
%
%/°C
%
ppm/°C
%/V
V
sec
ms
Cycles
Years
μA
μA
pF
μA
μA
V
V
V
V
V
V
pF
pF
kHz
%
MHz
MHz
ms
ms
μs
μs
ms

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