ADUC7061BCPZ32 Analog Devices Inc, ADUC7061BCPZ32 Datasheet - Page 64

• Manufacturer Part Number: ADUC7061BCPZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Package: 32LFCSP EP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 10.24 MHz
• Operating Supply Voltage: 2.5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 14
• Interface Type: I2C/SPI/UART
• On-chip Adc: 2(4-chx24-bit)
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7060/ADuC7061
IRQCLRE Register
Name:
Address:
Default value:
Access:
IRQCLRE
0xFFFF0038
0x00000000
Read and write
Rev. B | Page 64 of 108
Table 77. IRQCLRE MMR Bit Designations
Bit
31:20
19
18
17:15
14
13
12:0
Name
Reserved
IRQ3CLRI
IRQ2CLRI
Reserved
IRQ1CLRI
IRQ0CLRI
Reserved
Description
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the IRQ3
interrupt service routine to clear an edge
triggered IRQ3 interrupt.
A 1 must be written to this bit in the IRQ2
interrupt service routine to clear an edge
triggered IRQ2 interrupt.
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the IRQ1
interrupt service routine to clear an edge
triggered IRQ1 interrupt.
A 1 must be written to this bit in the IRQ0
interrupt service routine to clear an edge
triggered IRQ0 interrupt.
These bits are reserved and should not be
written to.