DSPIC33FJ32MC202-E/MM Microchip Technology, DSPIC33FJ32MC202-E/MM Datasheet - Page 113

• Manufacturer Part Number: DSPIC33FJ32MC202-E/MM
• Description: 16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices provide the ability to manage power consumption
by selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked
constitutes
dsPIC33FJ32MC202/204
devices can manage power consumption in four different
ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
9.1
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices allow a wide range of clock frequencies to be
selected under application control. If the system clock
configuration is not locked, users can choose
low-power or high-precision oscillators by simply
changing the NOSC bits (OSCCON<10:8>). The
process of changing a system clock during operation,
as well as limitations to the process, are discussed in
more
Configuration”.
EXAMPLE 9-1:
© 2011 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
detail
of the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices. It is not
intended
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog Timer and
Power Savings Modes” (DS70196) the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
lower
in
PWRSAV INSTRUCTION SYNTAX
to
Section 8.0
and
be
; Put the device into SLEEP mode
; Put the device into IDLE mode
consumed
a
dsPIC33FJ16MC304
comprehensive
“Oscillator
power.
in
9.2
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices have two special power-saving modes that are
entered through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and halts
all code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1
The following occur in Sleep mode:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate,
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
• Any peripheral that requires the system clock
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
since the system clock source is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
source for its operation is disabled.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
Example
9-1.
DS70283H-page 113