DSPIC33FJ32MC202-E/MM Microchip Technology, DSPIC33FJ32MC202-E/MM Datasheet - Page 206

• Manufacturer Part Number: DSPIC33FJ32MC202-E/MM
• Description: 16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 20-3:
DS70283H-page 206
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-13
bit 12-8
bit 7-0
Note 1:
R/W-0
ADRC
U-0
2:
This bit only used if AD1CON1<7:5> (SSRC2:0) = 111.
This bit is not used if AD1CON3<15> (ADRC) = 1.
ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from system clock
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits
11111 = 31 T
•
•
•
00001 = 1 T
00000 = 0 T
ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = Reserved
•
•
•
•
01000000 = Reserved
00111111 = T
•
•
•
00000010 = T
00000001 = T
00000000 = T
U-0
U-0
—
AD1CON3: ADC1 CONTROL REGISTER 3
AD
AD
AD
W = Writable bit
‘1’ = Bit is set
CY
CY
CY
CY
· (ADCS<7:0> + 1) = 64 · T
· (ADCS<7:0> + 1) = 3 · T
· (ADCS<7:0> + 1) = 2 · T
· (ADCS<7:0> + 1) = 1 · T
R/W-0
U-0
—
R/W-0
R/W-0
ADCS<7:0>
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CY
CY
CY
CY
R/W-0
R/W-0
(2)
(2)
= T
= T
= T
= T
AD
AD
AD
AD
SAMC<4:0>
R/W-0
R/W-0
(1)
© 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0